Abstract: An organic light-emitting display and a method of manufacturing the organic light-emitting display are disclosed. In one embodiment, the organic light-emitting display includes: i) a pixel electrode disposed on a substrate, ii) an opposite electrode disposed opposite to the pixel electrode, iii) an organic emission layer disposed between the pixel electrode and the opposite electrode; a light-scattering portion disposed between the substrate and the organic emission layer, including a plurality of scattering patterns for scattering light emitted from the organic emission layer in insulating layers having different refractive indexes. The display may further include a plurality of light absorption portions disposed between the light-scattering portion and the organic emission layer to correspond to the scattering patterns.

Abstract: A heat radiation component configured to be provided through a thermal interface material on a semiconductor device mounted on a board includes a first layer to be positioned on a first side and a second layer stacked on the first layer to be positioned on a second side farther from the semiconductor device than the first side. The coefficient of thermal expansion of the second layer is lower than the coefficient of thermal expansion of the first layer.

Abstract: A display device capable of suppressing decrease in capacitance and capable of reducing area even when a capacitor unit is repaired is provided. A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in an SD electrode layer and a second capacitor electrode provided in a GM electrode layer; a backup capacitor electrode provided in the TM electrode layer; a disconnect-able portion at which a connection between the first capacitor electrode and the power line can be disconnected; and a connectable portion at which the backup capacitor electrode and the power line can be connected, and the disconnect-able portion and the connectable portion overlap in a stacking direction.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: A pixel in the panel includes sub-pixels 100a, 100b, and 100c. Non-light-emitting cells 100d and 100e are provided between the pixel and adjacent pixels on both sides thereof, respectively. The organic light-emitting layer of sub-pixel 100a and non-light-emitting cell 100d are separated by bank 105a. Similarly, the organic light-emitting layer of sub-pixel 100c and non-light-emitting cell 100e are separated by bank 105d; the organic light-emitting layers of sub-pixels 100a and 100b are separated by bank 105b; and the organic light-emitting layers of sub-pixels 100b and 100c are separated by bank 105c. Inclination angle ?aa of sidewall 105aa of bank 105a adjacent to sib-pixel 100a and inclination angle ?dc of sidewall 105dc of bank 105d adjacent to sib-pixel 100c are larger than other inclination angles ?ba, ?bb, ?cb, and ?cc.

Abstract: Certain example embodiments of this invention relate to patterned glass that can be used as a cylindrical lens array in a concentrated photovoltaic application, and/or methods of making the same. In certain example embodiments, the lens arrays may be used in combination with strip solar cells and/or single-axis tracking systems. That is, in certain example embodiments, lenses in the lens array may be arranged so as to concentrate incident light onto respective strip solar cells, and the entire assembly may be connected to a single-axis tracking system that is programmed to follow the East-West movement of the sun. A low-iron glass may be used in connection with certain example embodiments. Such techniques may advantageously help to reduce cost per watt related, in part, to the potentially reduced amount of semiconductor material to be used for such example embodiments.

Abstract: A non-light-emitting cell 100c is provided between pixels 100a and 100b. Ink for forming an organic light-emitting layer is dripped substantially simultaneously into sub-pixels 100a1, 100a2, and 100a3 in the pixel 100a and a sub-pixel 100b1 in the pixel 100b. On the other hand, such ink is not dripped into the non-light-emitting cell 100c since the organic light-emitting layer is not formed in the non-light-emitting cell 100c. In a bank 105d, an inclination angle ?d3 of a wall 105d3 facing the sub-pixel 100a3 is larger than an inclination angle ?dc of a wall 105dc facing the non-light-emitting cell 100c. Similarly, in a bank 105e, an inclination angle ?e1 of a wall 105e1 facing the sub-pixel 100b1 is larger than an inclination angle ?ec of a wall 105ec facing the non-light-emitting cell 100c.

Abstract: A non-light-emitting cell 100c is provided between pixels 100a and 100b. In formation of the light-emitting cell 100a, ink for forming an organic light-emitting layer is dripped into sub-pixels 100a1, 100a2, 100a3 in this order. This also applies to the light-emitting cell 100b. However, such ink is not dripped into the non-light-emitting cell 100c since the organic light-emitting layer is not formed in the non-light-emitting cell 100c. Regarding a bank 105d between the sub-pixel 100a3 and the non-light-emitting cell 100c, an inclination angle ?d3 of a wall 105d3 is larger than an inclination angle ?dc of a wall 105dc. On the other hand, regarding a bank 105e between the sub-pixel 100b1 and the non-light-emitting cell 100c, an inclination angle ?e1 of a wall 105e1 is equivalent to an inclination angle ?ec of a wall 105ec.

Abstract: A non-light-emitting cell 100c is provided between pixels 100a and 100b. In formation of the pixel 100a, ink for forming an organic light-emitting layer is dripped into sub-pixels 100a1, 100a2, 100a3 in this order. This also applies to the pixel 100b. However, such ink is not dripped into the non-light-emitting cell 100c since the organic light-emitting layer is not formed in the non-light-emitting cell 100c. Regarding banks 105c and 105d defining the sub-pixel 100a3 of the pixel 100a, an inclination angle ?d3 of a wall 105d3 of the bank 105d is larger than an inclination angle ?c3 of a wall 105c3 of the bank 105c. Meanwhile, regarding banks 105e and 105f defining the sub-pixel 100b1, an inclination angle ?e1 of a wall 105e1 of the bank 105e is equivalent to an inclination angle ?f1 of a wall 105f1 of the bank 105f.

Abstract: A non-light-emitting cell 100c is provided between pixels 100a and 100b. Ink for forming an organic light-emitting layer is dripped substantially simultaneously into sub-pixels 100a1, 100a2, and 100a3 in the pixel 100a and a sub-pixel 100b1 in the pixel 100b. On the other hand, such ink is not dripped into the non-light-emitting cell 100c since the organic light-emitting layer is not formed in the non-light-emitting cell 100c. Regarding two banks 105c and 105d defining the sub-pixel 100a3, an inclination angle ?d3 of a wall 105d3 of the bank 105d is larger than an inclination angle ?c3 of a wall 105c3 of the bank 105c. Similarly, regarding banks 105e and 105f defining the sub-pixel 100b1, an inclination angle ?e1 of a wall 105e1 of the bank 105e is larger than an inclination angle ?f1 of a wall 105f1 of the bank 105f.

Abstract: A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in a GM electrode layer and a second capacitor electrode connected to a line and provided in an SD electrode layer; a backup capacitor element having a first backup capacitor electrode provided in the GM electrode layer and a second backup capacitor electrode connected to the power line and provided in the SD electrode layer; a disconnect-able portion at which a connection between the second capacitor electrode and the line can be disconnected; and a connectable portion at which the first backup capacitor electrode and the line can be connected, and the disconnect-able portion and the connectable portion are arranged at a position in which the disconnect-able portion and the connectable portion overlap in a stacking direction.

Abstract: The semiconductor device includes a semiconductor substrate of a first type. A layer of semiconductor material of a second type is disposed on the semiconductor substrate. A first well and a second well are disposed on the layer. A third well is disposed on the layer between the first and second wells. A memory cell, including a first and a second plurality of transistors of the second type and a third plurality of transistors of the first type, is formed in the first, second, and third wells. The first plurality of transistors is formed in the first well, the second plurality of transistors is formed in the second well, and the third plurality of transistors is formed in the third well. The layer and the third well are configured to isolate the first and second wells from each other and from the semiconductor substrate.

Abstract: A semiconductor package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, and possessing a recess which is defined on the upper surface; and a semiconductor chip mounted to the upper surface of the substrate, having one surface which faces the upper surface and the other surface which faces away from the one surface, and warped in a smile shape such that a warped edge portion of the semiconductor chip is inserted into the recess.

Abstract: A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.