Abstract: An array includes a substrate having a frontside surface and a backside surface. A backside cavity is formed in the backside surface. Backside through vias extend through the substrate from the frontside surface to the backside surface. Embedded component through vias extend through the substrate from the frontside surface to the backside cavity. An embedded component is mounted within the backside cavity and coupled to the embedded component through vias. In this manner, the embedded component is embedded within the substrate.

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract: A semiconductor device includes a trench formed in a substrate, a first stacked structure formed in the trench and including a plurality of first material layers and a plurality of second material layers stacked alternately on top of each other, and a transistor located on the substrate at a height corresponding to a top surface of the first stacked structure.

Abstract: The present invention relates to a quantum dot light emitting element which can form a quantum light emitting layer configured of charge transporting particles and quantum dots and a charge transporting layer in a solution process, to reduce process expense, and a method for manufacturing the same. The quantum dot light emitting element includes a substrate, an anode formed on the substrate, a quantum light emitting layer formed on the anode, the quantum light emitting layer having charge transporting particles and quantum dots mixed therein, and a cathode formed on the quantum light emitting layer.

Abstract: Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor.

Abstract: A light emitting device includes a first section and a second section. The first section includes a first semiconductor layer doped with a first dopant, a second semiconductor layer doped with a second dopant, and a first active layer between the first and second semiconductor layers, and the second section includes a third semiconductor layer disposed on the first section, and the third semiconductor layer having an exposed region, a fourth semiconductor layer disposed on the third semiconductor layer except for the exposed region, and a second active layer between the third and fourth semiconductor layers, a first electrode disposed on the first semiconductor layer, a second electrode disposed on the fourth semiconductor layer and a third electrode inserted into a hole in the exposed region and disposed on the exposed region and the second semiconductor layer, the third electrode electrically connected to the second and third semiconductor layers.

Abstract: Methods for fabricating FinFET integrated circuits with uniform fin height and ICs fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins. A first oxide is formed between the fins. A first etch stop is deposited on the first oxide. A second oxide is formed on the first etch stop. A second etch stop is deposited on the second oxide. A third oxide is deposited overlying the second etch stop. An STI extends from at least a surface of the substrate to at least a surface of the second etch stop overlying the fins to form a first active region and a second active region. The first etch stop overlying the fins is removed. The third oxide is removed to expose the second etch stop. A gate stack is formed overlying a portion of each of the fins.

Abstract: Semiconductor devices that include a trench with conductive material for connecting a VDMOS device to a LDMOS device are described. The semiconductor devices include a substrate having a first region and a second region, wherein the second region is disposed on the first region. A trench extends from a top surface of the second region to the first region. The semiconductor substrate includes a VDMOS device formed proximate to the top surface of the second region and a LDMOS device that is also formed proximate to the top surface of the second region. The drain region of the VDMOS device is electrically connected to the source region of the LDMOS device by way of a conductive material disposed in the trench.

Abstract: Through vias extend through a substrate between a frontside surface and a backside surface, the through vias comprising active surface ends at the frontside surface. A frontside redistribution structure is coupled to the active surface ends, the frontside redistribution structure exerting force on the frontside surface, e.g., due to a difference in the thermal coefficient of expansion (TCE) between the frontside redistribution structure and the substrate. To prevent warpage of the substrate, a backside warpage control structure is coupled to the backside surface of the substrate. The backside warpage control structure exerts an equal but opposite force to the force exerted by the frontside redistribution structure thus avoiding warpage of the substrate.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.

Abstract: The present teachings provide methods for forming organic layers for an organic light-emitting device (OLED) using an inkjet printing or thermal printing process. The method can further use one or more additional processes, such as vacuum thermal evaporation (VTE), to create an OLED stack. OLED stack structures are also provided wherein at least one of the charge injection or charge transport layers is formed by an inkjet printing or thermal printing method at a high deposition rate. The structure of the organic layer can be amorphous, crystalline, porous, dense, smooth, rough, or a combination thereof, depending on deposition parameters and post-treatment conditions. An OLED microcavity is also provided and can be formed by one of more of the methods.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost.

Abstract: An electronic device may include a temperature sensing semiconductor substrate, that may include a thermal sensor at an upper surface thereof, and a cooling semiconductor substrate having an upper surface coupled to a lower surface of the temperature sensing semiconductor substrate. The cooling semiconductor substrate may include a Peltier cooler. At least one of the temperature sensing semiconductor substrate and the cooling semiconductor substrate may have a cavity therein beneath the thermopile and aligned therewith.

Abstract: This disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a patterned stacked structure formed on a semiconductor substrate, the stacked structure comprising a silicon-containing semiconductor layer overlaying the semiconductor substrate, a gate dielectric layer overlaying the silicon-containing semiconductor layer and a gate layer overlaying the gate dielectric layer; and a doped epitaxial semiconductor layer on opposing sides of the silicon-containing semiconductor layer forming raised source/drain extension regions. Optionally, the silicon-containing semiconductor layer may be used as a channel region. According to this disclosure, the source/drain extension regions can be advantageously made to have a shallow junction depth (or a small thickness) and a high doping concentration.

Abstract: An organic EL panel includes reflective electrodes, a transparent electrode, organic light-emitting layers, and functional layers that are each provided between a corresponding one of the reflective electrodes and a corresponding one of the respective organic light-emitting layers. The film thicknesses of the respective functional layers of R, G, and B colors are each 60 nm or less such that a local maximum of light-emitting efficiency for a corresponding color is exhibited, and are substantially equal to each other. The optical distances between the respective organic light-emitting layers of the R, G, and B colors and the respective reflective electrodes are each 100 nm or less, and are substantially equal to each other.