Abstract: A LED (light emitting diode) packaging structure includes a base, a LED chip, a gel-blocking structure and a phosphor layer. The LED chip disposed on the base and electrically connected to the base. The LED chip having a substrate and a semiconductor layer formed on the substrate. The gel-blocking structure is disposed on the substrate of the LED chip and surrounding the semiconductor layer. The phosphor layer is filled within a space defined by the gel-blocking structure, the substrate and the semiconductor layer. The present invention also discloses a fabricating method of the LED packaging structure.

Abstract: A heterojunction bipolar transistor (HBT) device and system having electrostatic discharge ruggedness, and methods for making the same, are disclosed. An HBT device having electrostatic discharge ruggedness may include one or more emitter fingers including an emitter layer, a transition layer formed over the emitter layer, and an emitter cap layer formed over the transition layer.

Abstract: An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor having a gate electrode on a semiconductor substrate with a gate insulating film interposed between the semiconductor substrate and the gate electrode, and having a source region and a drain region formed in the semiconductor substrate on both sides of the gate electrode, the insulated gate field effect transistor including: a first diffusion layer of a P type formed in the semiconductor substrate at a position deeper than the source region and the drain region; and a second diffusion layer of the P type having a higher concentration than the first diffusion layer and formed in the semiconductor substrate at a position deeper than the first diffusion layer.

Abstract: Abstract of Disclosure A light emitting diode includes a substrate, an N-doped layer disposed on the substrate, a plurality of cathodes disposed between the N-doped layer and the substrate, an active layer disposed on the N-doped layer, a P-doped layer disposed on the active layer, and a plurality of anodes disposed on the P-doped layer. The cathodes are electrically connected to the N-doped layer, and the patterns of the cathodes are disconnected from each other. The anodes are electrically connected to the P-doped layer, and the patterns of the anodes are disconnected from each other. Each cathode and a corresponding anode form a loop, and each loop is an independent loop.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract: A light emitting device is provided. The light emitting device comprises: a reflective layer; and a semiconductor layer including a light emitting layer on the reflective layer. A distance between the reflective layer and a center of the light emitting layer corresponds to a constructive interference condition.

Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.

Abstract: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels.

Abstract: A solid-state imaging device capable of securing sufficient sensitivity and obtaining favorable characteristics is provided. The solid-state imaging device includes a charge-transfer portion 2 provided on one side of each column of light-receiving sensor portions 1, each forming a pixel, arranged in the form of a matrix and a transfer electrode of the charge-transfer portion 2 including a first transfer electrode formed of first electrode layers 3A and 3C and a second transfer electrode formed by electrically connecting first electrode layers 3B and 3D and a second electrode layer 4; the first electrode layers 3B and 3D in the second transfer electrode are independently formed in each of the charge-transfer portion 2; and the first transfer electrodes 3A and 3C and the second electrode layer 4 are laminated in a portion between pixels adjacent to each other in the direction of the charge-transfer portions 2.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: An optical component with integrated back monitor photodiode. The optical component includes a substrate doped with a first type dopant, such as an n-type dopant. The substrate has a trench with sloped walls. An optical source is disposed in the trench. An implant of a second type dopant, such as a p-type dopant, is in the substrate around at a least a portion of the optical source. The implant in the substrate in combination with the first type dopant in the substrate forms a diode.

Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.

Abstract: This invention relates to optoelectronic devices of improved efficiency. In particular it relates to light emitting diodes, photodiodes and photovoltaics. By careful design of periodic microstructures, e.g. gratings, associated with such devices more efficient light generation or detection is achieved.

Abstract: A MOSFET with a 0.7˜2.0 micrometers deep trench is formed by first carrying out a processing step of opening a trench in a semiconductor substrate. A thick insulator layer is then deposited in the trench such that the film at the bottom of the trench is much thicker than the sidewall of the trench. The insulator layer at the sidewall is then removed followed by the creation of composite dual layers that form the Gate Oxide. Another embodiment has the insulator layer deposited after Gate Oxide growth and stop at a thin Nitride layer which serves as stop layer during insulator pullback at trench sidewall and during Polysilicon CMP. Embodiments of the present invention eliminates weak spot at trench bottom corner encountered when Gate Oxide is grown in a 0.2 micrometers deep trench with thick bottom oxide.

Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.

Abstract: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench.

Abstract: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.

Abstract: In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling during mounting of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.

Abstract: A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.