Patents Examined by Adam D Houston
  • Patent number: 10931291
    Abstract: An array of devices, such as transceivers on a satellite, each use a phase locked loop (PLL) system to maintain a local oscillator at a particular frequency that is synchronized to a reference clock signal (RCS), maintaining tight timing discipline among the PLL systems. Each PLL system includes a first delta sigma modulator (DSM) and a second DSM. During a first time, a divider uses output from the first DSM to divide output from a voltage controlled oscillator of the PLL system. The output from the divider is provided as feedback to a phase frequency detector (PFD) of the PLL system and is also provided to the clock input of the first DSM. The PFD accepts as input the RCS. The second DSM uses the RCS as clock input. At a second time, the PLL system transitions from the divider using output from the first DSM to the second DSM.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: February 23, 2021
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Satwik Patnaik
  • Patent number: 10928447
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10931289
    Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 10924119
    Abstract: A clock data recovery circuit configured to receive an input data signal that includes an embedded clock signal includes a clock recovery circuit including a phase detector configured to detect a phase of the embedded clock signal and to generate a recovery clock signal from the input data signal based on the detected phase; and a data recovery circuit configured to generate a recovery data signal from the input data signal by using the recovery clock signal. The phase detector includes a sampling latch circuit configured to output a first sample signal and a second sample signal from the input data signal; and an edge detection circuit configured to generate a phase control signal based on the first sample signal and the second sample signal and output the phase control signal in a period in which the second sample signal is output from the sampling latch circuit.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Geumyoung Tak
  • Patent number: 10916571
    Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: February 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10917007
    Abstract: An apparatus for electric power conversion includes a converter having a regulating circuit and switching network. The regulating circuit has magnetic storage elements, and switches connected to the magnetic storage elements and controllable to switch between switching configurations. The regulating circuit maintains an average DC current through a magnetic storage element. The switching network includes charge storage elements connected to switches that are controllable to switch between plural switch configurations. In one configuration, the switches forms an arrangement of charge storage elements in which at least one charge storage element is charged using the magnetic storage element through the network input or output port. In another, the switches form an arrangement of charge storage elements in which an element discharges using the magnetic storage element through one of the input port and output port of the switching network.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: February 9, 2021
    Assignee: pSemi Corporation
    Inventor: David M. Giuliano
  • Patent number: 10911054
    Abstract: A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 2, 2021
    Assignee: Huawei International Pte. Ltd.
    Inventors: Theng Tee Yeo, Xuesong Chen, Rui Yu, Liu Supeng, Chao Yuan
  • Patent number: 10903538
    Abstract: A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminated and high, homogenous integration is achieved. Interconnections between the distributed inductance and the distributed capacitance are tailored to leverage a parasitic inductance of the distributed capacitance to increase the overall inductance of the distributed LC filter structure. Similarly, the interconnections are tailored to leverage a parasitic capacitance resulting from the distributed inductance to add up with the distributed capacitance augmenting the overall capacitance of the structure.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 26, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Frédéric Voiron, Mohamed Mehdi Jatlaoui
  • Patent number: 10903740
    Abstract: The present subject matter relates to charge pump devices, systems, and methods in which a first plurality of series-connected charge-pump stages is connected between a supply voltage node and a first circuit node, wherein the first plurality of charge-pump stages are operable to produce a first electrical charge at the first circuit node, the first electrical charge having a first polarity; and a second plurality of series-connected charge-pump stages is connected between the supply voltage node and a second circuit node, wherein the second plurality of charge-pump stages are operable to produce a second electrical charge at the second circuit node, the second electrical charge having a second polarity.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: January 26, 2021
    Assignee: WISPRY, INC.
    Inventors: Arthur S. Morris, III, Vincent Cheung, David Zimlich
  • Patent number: 10895589
    Abstract: A semiconductor device for monitoring a reverse voltage is provided. The semiconductor device includes an intellectual property having an input node and an output node; a passive component connected between the output node and a potential; a monitoring circuit connected to the input node and the output node and powered by a driving power, the monitoring circuit monitoring a difference between an input level at the input node and an output level at the output node to detect a reverse voltage across the intellectual property. The driving power is provided by the output node.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-han Choi, Tae-hwang Kong, Kwang-ho Kim, Sang-ho Kim, Se-Ki Kim, Jun-hyeok Yang, Sung-yong Lee, Yong-jin Lee
  • Patent number: 10892746
    Abstract: A system includes an input voltage supply. The system also includes a switching converter coupled to the input voltage supply and configured to provide an output voltage based on a switch on-time. The system also includes a switch on-time controller for the switching converter. The switch on-time controller includes an analog-to-digital converter (ADC) and a delay line coupled to the ADC. The switch on-time controller also includes a delay line modulator coupled to the delay line and configured to determine an amount of times the delay line is used to determine the switch on-time.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 12, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Thomas Lynch, Stefan Wlodzimierz Wiktor
  • Patent number: 10892764
    Abstract: A delay locked loop device (DLL) and an update method therefor are provided. The DLL device includes a DLL and an update circuit. The DLL is enabled according to an enable signal, thereby delaying an input clock to provide a delayed clock. The update circuit includes a flag generating circuit and an enable circuit. The flag generating circuit provides an update flag based on a default time interval. The enable circuit triggers the enable signal to a first logic level according to the update flag, and transitions the enable signal from the first logic level to a second logic level before the end of the default time interval. The default time interval is shorter than the refresh cycle of the memory.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 12, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Shinya Okuno
  • Patent number: 10893586
    Abstract: A Light Emitting Diode (LED) light includes a bridge rectifier configured to be powered by an alternating current power source and to produce a rectified output. Control circuitry couples to the bridge rectifier and is configured to produce a shunt signal when the rectified output is less than a threshold voltage. A series connected Light Emitting Diode (LED) string includes a first group of LEDs and a second group of LEDs. A switch couples to a first side of the second group of LEDs and is controlled by the shunt signal to deactivate the second group of LEDs. The control circuitry may include a ratio metric series resistor string configured to sense a proportion of the rectified output and an inverter configured to generate the shunt signal based on the proportion of the rectified output.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: January 12, 2021
    Assignee: AUSTIN IP PARTNERS
    Inventors: Mathew A. Rybicki, Daniel Patrick Mulligan
  • Patent number: 10886903
    Abstract: In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: January 5, 2021
    Assignee: Apple Inc.
    Inventor: Harsha Krishnamurthy
  • Patent number: 10879193
    Abstract: Various circuit board systems and methods of use and manufacture thereof are disclosed. A circuit board system can have a first circuit board including a substrate and a first component susceptible to electromagnetic interference carried by the substrate. The system can also include a second circuit board including a second substrate, and a shield engaged to the substrate of the first component, the shield at least partially covering the first component and being configured to protect the first component from electromagnetic interference, wherein the shield couples the substrate of the first circuit board to the substrate of the second circuit board.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 29, 2020
    Assignee: Snap Inc.
    Inventors: Stephen Andrew Steger, Emily Lauren Clopp
  • Patent number: 10873333
    Abstract: Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Rotem Avivi, Michael Kerner, Yair Dgani
  • Patent number: 10867258
    Abstract: Apparatus and methods for removing leakage from a qubit. In one aspect, an apparatus includes one or more qubits, wherein each qubit facilitates occupation of at least one of a plurality of qubit levels, the qubit levels including two computational levels and one or more non-computational levels that are each higher than the computational levels, wherein the qubit facilitates transitions between qubit levels associated with a corresponding transition frequency; a cavity, wherein the cavity defines a cavity frequency; one or more couplers coupling each qubit to the cavity; one or more couplers coupling the cavity to an environment external to the one or more qubits and the cavity; a frequency controller that controls the frequency of each qubit such that, for each qubit, the frequency of the qubit is adjusted relative to the cavity frequency such that a population of a non-computational level is transferred to the cavity.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Google LLC
    Inventor: Rami Barends
  • Patent number: 10855259
    Abstract: The present disclosure relates to a micromechanical displacement logic, signal propagation system that makes use of first and second bistable elements, and first and second mounting structures arranged adjacent opposing surfaces of the first bistable element. A plurality of pivotal lever arms are used to support the first bistable element in either one of two positions of equilibrium. A support structure and a compressible flexure element disposed between the support structure and the first mounting structure apply a preload force to the first mounting structure, which imparts the preload force to the first bistable element. The first bistable element is moveable from one of the two stable equilibrium positions to the other in response to an initial signal applied thereto.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: December 1, 2020
    Assignees: Lawrence Livermore National Security, LLC, The Regents of the University of California
    Inventors: Robert Matthew Panas, Logan Bekker, Julie Mancini, Andrew Pascall, Jonathan Hopkins, Amin Farzaneh
  • Patent number: 10855295
    Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Jahanshir Javanifard
  • Patent number: 10847979
    Abstract: A charging and communication system includes a potential output terminal for supplying power to a to-be-charged device; a first controller for generating a first control signal; and a first potential switching module for switching a first potential and a second in response to the first control signal. At least one of the first potential and the second potential is a charging potential, so as to supply power to the to-be-charged device. The first potential and the second potential are not equal, so as to communicate information to the to-be-charged device. The complexity of the hardware circuit structure is reduced. The stability and reliability of the circuit structure is improved.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 24, 2020
    Assignee: ZHUHAI JIELI TECHNOLOGY CO., LTD
    Inventors: Shusheng Long, Guangjun Luo