Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.

Abstract: In some implementations, a radiofrequency down converter comprises an input port to receive a radiofrequency input signal, and the down converter includes a first bandpass filter configured to filter the input signal. The down converter includes a mixer stage coupled to the bandpass filter, the mixer stage being configured to generate a mixer output signal by processing the filtered input signal using a gain adjustment device, one or more amplifiers, and a mixer. The down converter includes a signal adjustment stage coupled to receive the mixer output signal, the signal adjustment stage comprising: a temperature compensation device configured to compensate for changes in signal gain due to changes in temperature; a second bandpass filter; a gain adjustment device; one or more amplifiers; and a low pass filter. The down converter comprises an output port coupled to output an adjusted mixer output signal from the signal adjustment stage.

Abstract: A wireless power transmission system includes: an electrical energy-receiving oscillation circuit including an electrical energy-receiving coil L2 and a compensation capacitor C2 connected in series, the electrical energy-receiving coil L2 sensing an alternating magnetic field and generating an induction current accordingly; a rectifier circuit connected to two ends of the electrical energy-receiving oscillation circuit; and a modulation circuit including multiple modulation sub-circuits, each of the modulation sub-circuits being separately connected to the electrical energy-receiving oscillation circuit, and the modulation circuit receiving a drive signal used to select a modulation sub-circuit matching a power level of a load of the wireless power transmission receiving circuit to operate, and the modulation sub-circuits receive, during a communication process, a communication signal and load the communication signal on a carrier signal to perform modulation.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: Disclosed are techniques for using a sense amplifier for the voltage path having an adjustable gain and a current amplifier for the current path having an adjustable sample-hold interval for demodulation of in-band ASK data in power transmitting devices of a wireless charging system. The sample-hold interval may be adjusted as a function of the error rate of the demodulated data and used to sample the modulated current when the adjustable gain of the voltage path is not able to track the modulated voltage. The adjustable sample-hold may function as a variable reference of a comparator used to compare the sampled current to generate the sensed current. A controller may flexibly adjust the gain, adjust the sample-hold interval, and/or select the sensed voltage or the sensed current path for further filtering, demodulation, decoding, and processing depending on the error rate under various loading, coupling scenarios, and phases of power transfer.

Abstract: An improved electro acoustic RF filter (FC) is provided. The RF filter comprises an electro acoustic resonator (EAR) connected between an input port and an output port, an impedance element and a damping and/or dissipation element (DE) in mechanical contact to the impedance element. The damping and/or dissipation element is provided and configured to remove acoustic energy from the impedance element which has a similar construction as the resonator on the same substrate. With such a construction an acoustically inactive impedance element (AIIE) is obtained.

Abstract: A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

Abstract: An on-board electrical network (4) of a motor vehicle (2) has a first voltage circuit (I) and a second voltage circuit (II), wherein the first voltage circuit has a first operating voltage higher than a second operating voltage in the second voltage circuit. The first voltage circuit is connected to the second voltage circuit via a DC voltage converter (8). The first voltage circuit has a battery (10) and the second voltage circuit has a main battery (12) and an auxiliary voltage source (14). By means of a first switching element (16) and a second switching element (18) at least one of transmission control unit (20) and/or integrated hybrid controller (22) are supplied with electrical energy from the main battery (12) and/or the auxiliary voltage source (14). Control unit (20) and/or hybrid controller (22) can be selectably disconnected from either the main battery (12) and/or the auxiliary voltage source (14).

Abstract: An acoustic filter includes a piezoelectric plate on a substrate. Portions of the piezoelectric plate form one or more diaphragms, each diaphragm spanning a respective cavity in the substrate. A conductor pattern on a front surface of the piezoelectric plate includes interdigital transducers (IDTs) of acoustic resonators including a shunt resonator and a series resonator. Interleaved fingers of each IDT are on a diaphragm of the one or more diaphragms. A first dielectric layer with a first thickness is between the fingers of the IDT of the shunt resonator, and a second dielectric layer with a second thickness less than the first thickness is between the fingers of the IDT of the series resonator. The piezoelectric plate and the IDTs are configured such that radio frequency signals applied to the IDTs excite respective primary shear acoustic modes within the diaphragms.

Abstract: A method includes producing a plurality of TX LO signals by a first LO generator comprising a first frequency doubler and a first frequency divider, the first frequency doubler configured to receive a VCO signal having a first frequency and generate a first signal fed into the first frequency divider, the first signal having a second frequency that is twice the first frequency, producing a plurality of MRX LO signals by a second LO generator comprising a second frequency doubler and a second frequency divider, the second frequency doubler configured to receive the VCO signal and generate a second signal fed into the second frequency divider, the second signal having the second frequency, configuring the TX to operate at a first LO frequency equal to the second frequency, and configuring the MRX to operate at a second LO frequency equal to the first frequency through disabling the second frequency doubler.

Abstract: A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

Abstract: A high-frequency component for radar-based distance measurement comprises: a semiconductor component configured to generate electrical high-frequency signals; and coupling element configured as a substrate-integrated waveguide and electrically contacted by the semiconductor component as to couple the high-frequency signals as radar signals into a hollow waveguide of the high-frequency component, the hollow waveguide being in galvanic contact with the coupling element such that no defined distance between the hollow waveguide and the coupling element must be set to achieve an efficient coupling out of the high-frequency signal into the hollow waveguide. The galvanic contact thereby enables a simple manufacture of the high-frequency component and a compact and accurate distance measuring device using the high-frequency component.

Abstract: An electro acoustic resonator is provided. The resonator has a gap short structure (GSS) to electrically short at least an area of the transversal gap to suppress transversal gap mode excitations. The gap short structure may be provided by a conductive stripe in the gap and parallel to or inclined with respect to the bus bar (BB) shorting adjacent IDT fingers. Additional connectors between the stripe and the bus bar may be provided. The connectors may have different pitch or metallization ratio with respect to the ID fingers. The connectors may be offset from the position of the fingers and my be inclined with respect to the bus bars. Multiple parallel stripes in the gap may provide a transversal reflector. By using a gap short structure a further improved transversal mode suppression of piston mode designs can be achieved.

Abstract: Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.

Abstract: Filter devices are disclosed. A filter device includes a piezoelectric plate comprising a supported portion, a first diaphragm, and a second diaphragm. The supported portion is attached to a substrate and the first and second diaphragms spans respective cavities in the substrate. A first interdigital transducer (IDT) has interleaved fingers on the first diaphragm. A second interdigital transducer (IDT) has interleaved fingers on the second diaphragm. A first dielectric layer is between the interleaved fingers of the first IDT, and a second dielectric layer is between the interleaved fingers of the second IDT. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer. The piezoelectric plate and the first and second IDTs are configured such that radio frequency signals applied to first and second IDTs excite primary shear acoustic modes in the respective diaphragms.

Abstract: A frequency synthesizer employs a combination of a low divide ratio divider phase-locked loop (PLL) and a wide band, on-chip voltage-controlled oscillator (VCO). To reduce phase noise, low divide ratio phase detection is employed. By using the off-chip PLL with a bank of on-chip VCOs, the frequency synthesizer may have enhanced frequency stability and avoid having to include an acquisition circuit. A separation between the PLL and VCO may reduce integer boundary spurs (IBS) eliminating or reducing a need for a filter bank and switches reducing a complexity of the frequency synthesizer.

Abstract: Examples described herein provide a method that includes determining whether a vehicle is operating in a first high voltage mode or a second high voltage mode. The method further includes, responsive to determining that the vehicle is operating in the first high voltage mode, providing electric power to an electric motor at a first high voltage and providing electric power to an auxiliary device at a second high voltage that is different than the first high voltage. The method further includes, responsive to determining that the vehicle is operating in the second high voltage mode, providing electric power to the electric motor at the second high voltage and providing electric power to the auxiliary device at the second high voltage.

Abstract: A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103).

Abstract: A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminated and high, homogenous integration is achieved. Interconnections between the distributed inductance and the distributed capacitance are tailored to leverage a parasitic inductance of the distributed capacitance to increase the overall inductance of the distributed LC filter structure. Similarly, the interconnections are tailored to leverage a parasitic capacitance resulting from the distributed inductance to add up with the distributed capacitance augmenting the overall capacitance of the structure.