Patents Examined by Adam S Bowen
  • Patent number: 11515216
    Abstract: A semiconductor structure is received that has a first and second fins. A first epitaxial feature is formed on the first fin and has a first type dopant. A first capping layer is formed over the first epitaxial feature. A second epitaxial feature is formed on the second fin and has a second type dopant different from the first type dopant. A first metal is deposited on the second epitaxial feature and on the first capping layer. A first silicide layer is formed from the first metal and the second epitaxial feature, and a second capping layer is formed from the first metal and the first capping layer. The second capping layer is selectively removed. A second metal is deposited on the first epitaxial feature and over the second epitaxial feature. A second silicide layer is formed from the second metal and the first epitaxial feature.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11515215
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and forming a first plurality of protruding fins and a second protruding fin over the isolation regions. The first plurality of protruding fins include an outer fin farthest from the second protruding fin, and an inner fin closest to the second protruding fin. The method further includes etching the first plurality of protruding fins to form first recesses, growing first epitaxy regions from the first recesses, wherein the first epitaxy regions are merged to form a merged epitaxy region, etching the second protruding fin to form a second recess, and growing a second epitaxy region from the second recess. A top surface of the merged epitaxy region is lower on a side facing toward the second epitaxy region than on a side facing away from the second epitaxy region.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shahaji B. More
  • Patent number: 11508624
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jhe-Ching Lu, Bao-Ru Young, Yen-Sen Wang, Tsung-Chieh Tsai
  • Patent number: 11502088
    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: November 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Shu-Wei Yeh, Chang-Hung Chen
  • Patent number: 11502005
    Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11502079
    Abstract: An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Hyunwoo Park, Peijie Feng
  • Patent number: 11495502
    Abstract: The disclosure provides a manufacturing method for a fin field-effect transistor. The method to make the fin field-effect transistor comprises: forming a fin structure and a gate structure spanning on the fin structure on a substrate; and forming a source-drain region on the fin structure, which comprises: forming an epitaxial layer; and forming a sacrificial layer on the surface of the epitaxial layer to prevent the epitaxial layer from being lost in the subsequent removal steps.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 8, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventors: Huojin Tu, Jueyang Liu, Zhanyuan Hu
  • Patent number: 11495592
    Abstract: An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bonghyun Lee
  • Patent number: 11489057
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang, Tzer-Min Shen, Pinyen Lin, Sung-Li Wang
  • Patent number: 11489075
    Abstract: In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chandrashekhar Prakash Savant
  • Patent number: 11482553
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes at least one pixel, and each pixel includes N subpixels, wherein each of the subpixels comprises a detection region, two first conductive contacts, wherein the detection region is between the two first conductive contacts, wherein N is a positive integer and is ?2.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 25, 2022
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lu Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang
  • Patent number: 11482518
    Abstract: A semiconductor structure includes a substrate having first and second wells of first and second conductivity types respectively. From a top view, the first and second wells extend lengthwise along a first direction, the first and second wells each includes a protruding section that protrudes along a second direction perpendicular to the first direction and a recessed section that recedes along the second direction. The protruding section of the first well fits into the recessed section of the second well, and vice versa. The semiconductor structure further includes first source/drain features over the protruding section of the first well; second source/drain features over the second well; third source/drain features over the protruding section of the second well; and fourth source/drain features over the first well. The first and second source/drain features are of the first conductivity type. The third and fourth source/drain features are of the second conductivity type.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung Feng Chang, Chun-Chia Hsu, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 11476342
    Abstract: Semiconductor device includes substrate having fins, first S/D feature comprising first epitaxial layer contacting first fin, second epitaxial layer on first epitaxial layer, third epitaxial layer on second epitaxial layer, third epitaxial layer comprising center and edge portion higher than center portion, and fourth epitaxial layer on third epitaxial layer, second S/D feature adjacent first S/D feature and comprising first epitaxial layer contacting second fin, second epitaxial layer on first epitaxial layer of second S/D feature, third epitaxial layer on second epitaxial layer of second S/D feature, third epitaxial layer comprising center and edge portion higher than center portion of third epitaxial layer, center and edge portions of third epitaxial layer of first and second S/D features are merging, and fourth epitaxial layer on third epitaxial layer of second S/D feature, S/D contact covering edge and center portions of third epitaxial layers of first and second S/D features.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11469239
    Abstract: An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: October 11, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Channappa Desai, Sunil Sharma, Anne Srikanth, Pradeep Jayadev Kodlipet, Yandong Gao
  • Patent number: 11450751
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang
  • Patent number: 11450665
    Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11450605
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Patent number: 11444134
    Abstract: A light-emitting device includes a semi-transmissive reflection layer, a first reflection layer that is disposed in a first sub-pixel, a first pixel electrode that is disposed in the first sub-pixel, a first color filer that is disposed in the first sub-pixel, a second reflection layer that is disposed in a second sub-pixel, a second pixel electrode that is disposed in the second sub-pixel, a second color filter that is disposed in the second sub-pixel, the second color filter that is same color as the first color filter, a light-emitting functional layer, and an insulating layer that is disposed between the first reflection layer and the first pixel electrode, the light-emitting functional layer that is disposed between the second reflection layer and the second pixel electrode. A thickness of the insulating layer in the second sub-pixel is thicker than a thickness of the insulating layer in the first sub-pixel.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 13, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Koshihara, Jun Irobe
  • Patent number: 11430789
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure includes a base layer, an isolating layer over the base layer, and a stack of channel layers and first sacrificial layers alternately stacked over the isolating layer. The method further includes forming an isolation structure adjacent to sidewalls of the fin structure, wherein a top surface of the isolation structure is above a bottom surface of the isolating layer and below a top surface of the isolating layer. The method further includes depositing a second sacrificial layer over the isolation structure and over the sidewalls of the fin structure; etching the second sacrificial layer and the fin structure to form two source/drain trenches, wherein the source/drain trenches expose the base layer; partially removing the first and the second sacrificial layers through the source/drain trenches to form gaps; and depositing a dielectric spacer in the gaps.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11430790
    Abstract: An embodiment device includes: an isolation region on a substrate; a first fin extending above a top surface of the isolation region; a gate structure on the first fin; and an epitaxial source/drain region adjacent the gate structure, the epitaxial source/drain region having a first main portion and a first projecting portion, the first main portion disposed in the first fin, the first projecting portion disposed on a first sidewall of the first fin and beneath the top surface of the isolation region.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shahaji B. More