Patents Examined by Adam S Bowen
  • Patent number: 11171143
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin, a first semiconductor fin and a second dielectric fin over a substrate. The first semiconductor fin is between the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first gate electrode wrapping the first dielectric fin, a channel region of the first semiconductor fin and the second dielectric fin and a first source/drain structure over a source/drain portion of the first semiconductor fin, being in contact with and interposing the first dielectric fin and the second dielectric fin.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11164795
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sipeng Gu, Judson Holt, Haiting Wang, Bangun Indajang
  • Patent number: 11145701
    Abstract: A display device includes a plurality of pixels each including a first light emitting element with a first light reflecting layer, a second light emitting element with a second light reflecting layer, and a third light emitting element with a third light reflecting layer, arranged in a two-dimensional matrix. Each of the light emitting elements includes a first electrode, an organic layer, and a second electrode. Grooves that each have a light shielding layer are formed in a boundary region between the light emitting elements. A bottom of the first groove and a bottom of the third groove are located at a position higher than a top surface of the first light reflecting layer. A bottom of the second groove is located at a position higher than a top surface of the second light reflecting layer.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 12, 2021
    Assignee: Sony Corporation
    Inventor: Tomokazu Ohchi
  • Patent number: 11145729
    Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Meng-Chang Ho, Chung-Hao Chu, Tz-Hau Guo
  • Patent number: 11139239
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
  • Patent number: 11139231
    Abstract: A radio frequency module includes: a multilayer substrate that includes a plurality of insulator layers; an amplifying circuit that is provided on the multilayer substrate and amplifies a radio frequency signal; a power supply circuit that is provided on the multilayer substrate and supplies power to the amplifying circuit; a ground conductor that is a first conductor pattern having a ground potential and used in the amplifying circuit; and a ground conductor that is a second conductor pattern having a ground potential and used in the power supply circuit. The ground conductors are physically separated from each other and provided in internal layers of the multilayer substrate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 5, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Akifumi Honda
  • Patent number: 11133230
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate having a first region and a second region; a first semiconductor fin formed on the substrate within the first region; a second semiconductor fin formed on the substrate within the second region; a first liner layer disposed along a lower portion of the first semiconductor fin and a lower portion of the second semiconductor fin; a second liner layer disposed over the first liner layer in the second region, wherein the second liner layer is different from the first liner layer in composition; and an isolation feature disposed on the first liner layer in the first region and on the second liner layer in the second region, and separating lower portions of the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yu-Kuan Lin
  • Patent number: 11121205
    Abstract: A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 14, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Daegeun Lee, Kyung-Mok Lee, Wuhyen Jung
  • Patent number: 11114366
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first well region over a substrate, and an isolation structure over the first well region. The semiconductor structure also includes a first transistor over the first well region, and a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor. A top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11107775
    Abstract: The present disclosure provides a semiconductor device including a first semiconductor structure, a first connecting structure positioned on the first semiconductor structure, a second connecting structure positioned on the first connecting structure, and a second semiconductor structure positioned on the second connecting structure. The first connecting structure includes a plurality of first connecting contacts and a plurality of first supporting contacts positioned in a first connecting insulating layer. The second connecting structure includes a plurality of second connecting contacts and a plurality of second supporting contacts positioned in the second connecting insulating layer positioned on the first connecting structure. The plurality of first connecting contacts contact the plurality of second connecting contacts, forming signal-transmitting contacts.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 31, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11105928
    Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 31, 2021
    Assignee: Artilux, Inc.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Shu-Lu Chen, Yun-Chung Na, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang, Jung-Chin Chiang, Yen-Cheng Lu, Yen-Ju Lin
  • Patent number: 11107842
    Abstract: A pixel array substrate includes a substrate, a first patterned conductive layer, a pixel electrode layer, a semiconductor pattern layer, a first dielectric layer, a second patterned conductive layer, a second dielectric layer, and a common electrode layer. The first patterned conductive layer includes first and second scan lines, first and second gates, and first and second connection electrodes. The pixel electrode layer includes first and second pixel electrodes. The semiconductor pattern layer includes first and second patterns. The second patterned conductive layer includes first and second data lines, first and second sources, first and second drains, and a touch wire. The common electrode layer includes a common electrode and first and second transferring electrodes. The first transferring electrode is electrically connected to the first connection electrode and the first drain. The second transferring electrode is electrically connected to the second connection electrode and the second drain.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 31, 2021
    Assignee: Au Optronics Corporation
    Inventors: Yu-Min Chi, Sung-Yu Su, Chen-Feng Fan
  • Patent number: 11101446
    Abstract: A display apparatus includes a first display area including a first display unit configured to generate light and a first encapsulation unit disposed on the first display unit; a second display area including a second display unit configured to generate light and a second encapsulation unit disposed on the second display unit; and a through area disposed between the first display area and the second display area. The first encapsulation unit includes a first encapsulation layer covering a first side of an area of the first display unit corresponding to the through area. The second encapsulation unit includes a second encapsulation layer covering a second side of an area of the second display unit corresponding to the through area.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kinyeng Kang, Seungwook Chang, Jonghyun Choi
  • Patent number: 11101197
    Abstract: Leadframe systems and related methods. Specific implementations of leadframe systems may include a die pad, a semiconductor die coupled to the die pad, where the semiconductor die has a perimeter. A leadframe may be coupled over the die pad and the semiconductor die where the leadframe has a solder dam coupled around the semiconductor die and, the solder dam has a perimeter that corresponds with the semiconductor die The die pad may have no groove adjacent to the semiconductor die.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 24, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hiroshi Inoguchi, Isao Ochiai, Takayuki Taguchi
  • Patent number: 11088302
    Abstract: A light emitting device is disclosed. In an embodiment a light-emitting device includes a pixel comprising at least three sub-pixels, wherein a first sub-pixel includes a first conversion element having a green phosphor, wherein a second sub-pixel includes a second conversion element having a red phosphor and wherein a third sub-pixel is free of a conversion element, the third sub-pixel configured to emit blue primary radiation, wherein each sub-pixel has an edge length of at most 100 ?m, and wherein the light-emitting device is configured to enhance a gamut coverage of an emitted radiation.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 10, 2021
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Benjamin Daniel Mangum, David O'Brien, Britta Göötz
  • Patent number: 11079476
    Abstract: A light-receiving element includes an on-chip lens; an interconnection layer; and a semiconductor layer that is disposed between the on-chip lens and the interconnection layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit that is disposed at the periphery of the first voltage application unit, a second charge detection unit that is disposed at the periphery of the second voltage application unit, and a charge discharge region that is provided on an outer side of an effective pixel region. For example, the present technology is applicable to a light-receiving element that generates distance information in a ToF method, or the like.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 3, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tsutomu Imoto, Yuji Isogai, Takuya Maruyama, Takuro Murase, Ryota Watanabe, Takeshi Yamazaki
  • Patent number: 11081425
    Abstract: A semiconductor package includes a base wafer including a first substrate and at least one first through via electrode extending through the first substrate, and a first semiconductor chip provided on the base wafer. The first semiconductor chip includes a second substrate; and at least one second through via electrode extending through the second substrate. The at least one second through via electrode is provided on the at least one first through via electrode to be electrically connected to the at least one first through via electrode. A first diameter of the at least one first through via electrode in a first direction is greater than a second diameter of the at least one second through via electrode in the first direction.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 3, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gun-Ho Chang, Seung-Duk Baek
  • Patent number: 11075147
    Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Vivek Arora, Ken Pham
  • Patent number: 11075206
    Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 27, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kwanyong Lim, Youn Sung Choi, Ukjin Roh
  • Patent number: 11063207
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen