Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

Abstract: The present application discloses a method for manufacturing a fin field effect transistor, comprising: step 1: forming fins; step 2, forming first gate structures; and step 3, forming source and drain areas, comprising: step 31: forming a second hard mask layer; step 32: opening a formation area of FinFET, and performing the first time etching on the second hard mask layer; step 33: performing the second time etching to form first grooves in the fins, wherein the second time etching vertically and horizontally etches the isolation dielectric layer, when the second groove is formed next to the exposed surfaces of the isolation dielectric layer, the exposed surfaces of the fins and the first polysilicon gate, as the result, the second groove forms a bridge path; step 34: forming a sacrificial sidewall to fully fill the bridge path; and step 35: filling the first groove with an epitaxial layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin and a second dielectric fin over a substrate, a first semiconductor fin between the first dielectric fin and the second dielectric fin, and an insulating liner surrounding a lower portion of the first dielectric fin, a lower portion of the first semiconductor fin, and a lower portion of the second dielectric fin. The semiconductor structure also includes a first gate electrode surrounding an upper portion of the first dielectric fin and an upper portion of the first semiconductor fin.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a recess structure in a substrate and forming a first semiconductor layer over the recess structure. The process of forming the first semiconductor layer can include doping first and second portions of the first semiconductor layer with a first n-type dopant having first and second doping concentrations, respectively. The second doping concentration can be greater than the first doping concentration. The method can further include forming a second semiconductor layer over the second portion of the first semiconductor layer. The process of forming the second semiconductor layer can include doping the second semiconductor layer with a second n-type dopant.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a semiconductor substrate. Alternating layers of a first semiconductor layer and a second semiconductor layer are formed. The first semiconductor layer is formed of a first semiconductor material, the second semiconductor layer formed of a second semiconductor material different from the first semiconductor material. The alternating layers of the first semiconductor layer and the second semiconductor layer are patterned to form stacks of the alternating layers and to expose lateral edges of the alternating layers in the stacks. Under etch conditions, the lateral edges of the alternating layers in the stacks are exposed to etchant to selectively etch recesses in the lateral edges of the first semiconductor layer such that a size of the recesses is substantially uniform.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

Abstract: A display apparatus includes a first display area including a first display unit configured to generate light and a first encapsulation unit disposed on the first display unit; a second display area including a second display unit configured to generate light and a second encapsulation unit disposed on the second display unit; and a through area disposed between the first display area and the second display area. The first encapsulation unit includes a first encapsulation layer covering a first side of an area of the first display unit corresponding to the through area. The second encapsulation unit includes a second encapsulation layer covering a second side of an area of the second display unit corresponding to the through area.

Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

Abstract: A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

Abstract: An embodiment device includes: first fins protruding from an isolation region; second fins protruding from the isolation region; a first fin spacer on a first sidewall of one of the first fins, the first fin spacer disposed on the isolation region, the first fin spacer having a first spacer height; a second fin spacer on a second sidewall of one of the second fins, the second fin spacer disposed on the isolation region, the second fin spacer having a second spacer height, the first spacer height greater than the second spacer height; a first epitaxial source/drain region on the first fin spacer and in the first fins, the first epitaxial source/drain region having a first width; and a second epitaxial source/drain region on the second fin spacer and in the second fins, the second epitaxial source/drain region having a second width, the first width greater than the second width.

Abstract: Semiconductor devices and methods of forming semiconductor devices are described herein. A method includes forming a first fin and a second fin in a substrate. A low concentration source/drain region is epitaxially grown over the first fin and over the second fin. The material of the low concentration region has less than 50% by volume of germanium. A high concentration contact landing region is formed over the low concentration regions. The material of the high concentration contact landing region has at least 50% by volume germanium. The high concentration contact landing region has a thickness of at least 1 nm over a top surface of the low concentration source/drain region.

Abstract: A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI. The metal compound feature extends continuously from the top surface of the NEPI to the top surface of the PEPI. The semiconductor structure further includes a contact feature disposed on the metal compound feature and a via structure disposed over the contact feature.

Abstract: Integrated circuit (“IC”) layouts are disclosed for improving performance of memory arrays, such as static random access memory (“SRAM”). An exemplary IC device includes an SRAM cell and an interconnect structure electrically coupled to the SRAM cell. The interconnect structure includes a first metal layer electrically coupled to the SRAM cell that includes a bit line, a first voltage line having a first voltage, a word line landing pad, and a second voltage line having a second voltage that is different than the first voltage. The first voltage line is adjacent the bit line. The word line landing pad is adjacent the first voltage line. The second voltage line is adjacent the word line landing pad. A second metal layer is disposed over the first metal layer. The second metal layer includes a word line that is electrically coupled to the word line landing pad.