Abstract: Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked, and based on the confidence level being a first value, a predicted operation of the instruction, which is based on a predictor, is unconditionally performed. Further, based on the confidence level being a second value, a specified operation of the instruction, which is based on a determined condition, is conditionally performed.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

Abstract: Technique for analyzing memory areas based on local copies of a global counter by: (i) determining a plurality of currently-executing fast threads and a plurality of currently executed slow threads; (ii) intermittently incrementing a global counter variable to have a current global counter value; (iii) intermittently setting the local counter of the data set for each fast thread of the plurality of fast threads to be equal to the current global counter value; (iv) determining that no slow threads of the plurality of slow threads reference the first memory region; (v) assigning a free-after value to the first memory region; (vi) determining whether the free-after value of the first memory region is less than or equal to all of the local counters of the fast thread data sets of the plurality of fast threads; and (vii) de-allocating the first memory region.

Abstract: Techniques for increasing vector processing utilization and efficiency through use of unmasked lanes of predicated vector instructions for executing non-conflicting instructions are provided. In one aspect, a method of vector lane predication for a processor is provided which includes the steps of: fetching predicated vector instructions from a memory; decoding the predicated vector instructions; determining if a mask value of the predicated vector instructions is available and, if the mask value of the predicated vector instructions is not available, predicting the mask value of the predicated vector instructions; and dispatching the predicated vector instructions to only masked vector lanes.

Abstract: Technique for analyzing memory areas based on local copies of a global counter by: (i) determining a plurality of currently-executing fast threads and a plurality of currently executed slow threads; (ii) intermittently incrementing a global counter variable to have a current global counter value; (iii) intermittently setting the local counter of the data set for each fast thread of the plurality of fast threads to be equal to the current global counter value; (iv) determining that no slow threads of the plurality of slow threads reference the first memory region; (v) assigning a free-after value to the first memory region; (vi) determining whether the free-after value of the first memory region is less than or equal to all of the local counters of the fast thread data sets of the plurality of fast threads; and (vii) de-allocating the first memory region.

Abstract: Aspects of the disclosure provide a circuit that includes a first memory, a second memory and a comparator. The first memory is configured to store a plurality of values corresponding to a first plurality of ranges and generate an output value in response to a lookup key. The output value is indicative of the lookup key matching a stored value corresponding to a first range in the first plurality of ranges. The second memory is configured to store limiting values of a second plurality of ranges, and output a set of limiting values for a second range in association with the first range based on the output value of the first memory. The comparator is configured to compare the input value with the set of limiting values to determine whether the second range is inclusive of the lookup key.

Abstract: Various systems and methods for seeding a storage device. For example, a method involves accessing a policy that identifies a number of clients. The method then involves selecting a most recent backup image for each of the clients and copying the most recent backup images from a source storage device to a target storage device. Once a most recent backup image has been copied from the source storage device to the target storage device for each of the clients, the method switches a destination value in the policy from the source storage device to the target storage device.

Abstract: Methods, systems, and computer program products for tracking updates during memory migration. The method includes computer instructions for establishing communication from a source virtual machine to a target virtual machine, the source virtual machine including a memory. Contents of the memory on the source virtual machine are transmitted to the target virtual machine. The contents include a plurality of pages. Pages in the memory that are modified subsequent to being transmitted to the target virtual machine are tracked. The tracking includes creating a data structure having a plurality of bits corresponding to the pages in the memory, the bits indicating if the corresponding pages have been modified subsequent to being transmitted to the target virtual machine. The data structure also includes a first bit location index to identify the location of the first bit in the data structure that corresponds to a modified page.

Abstract: A manufacturing testing system includes an information handling system, a RAM memory device including a reserved physical RAM address space, non-volatile bootable disk, and a header for the reserved physical RAM address space. The head may include a non-volatile bootable disk signature, a start physical address, a length of reserved space, and a processor.

Abstract: Embodiments of the invention are directed to optimizing reconstruction of operation data in volatile memory of solid-state storage subsystems. In various embodiments, operation data is stored in the volatile memory with persistent backup data of the operation data in the non-volatile memory. In one embodiment, operation data includes a superblock table that is used to identify most or all groups of blocks (superblocks) within the storage device that certain firmware components operate on. Sometimes operation data in the volatile memory is lost or corrupted due to a power interruption or system shutdown. To optimize the reconstruction of the superblock table or other similar operation data in the volatile memory, embodiments of the invention use a “snapshot entry” to identify the latest entry information, allowing the controller to quickly identify the most updated physical locations of the operation data portions and complete the reconstruction in an efficient manner.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: A one-dimensional array is allocated in an in-memory cache for each column in a set of tabular data. The data type of each one-dimensional array is set to be the same as the data type of the corresponding column in the tabular data. Once the one-dimensional arrays have been allocated in memory, a portion of the data from each column in the tabular data is stored in a corresponding one-dimensional array. The tabular data stored in the one-dimensional arrays in the cache may then be utilized to generate an on-screen display of a portion of the tabular data.

Abstract: A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (AP) external to the primary coherent system. The CAPP includes a CAPP directory of contents of a cache memory in the AP that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. In response to the memory access request, the CAPP performs a first determination of a coherence state for the target address and allocates a master machine to service the memory access request in accordance with the first determination. Thereafter, during allocation of the master machine, the CAPP updates the coherence state and performs a second determination of the coherence state. The master machine services the memory access request in accordance with the second determination.

Abstract: A method and apparatus for providing shared caches. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, at least one bit may overlap tag bits and set index bits among bits of a memory address.

Abstract: A first data structure stores indications of storage locations that need to be copied for forming a consistency group. A second data structure stores indications of new host writes subsequent to starting a point in time copy operation to form the consistency group. Read access is secured to a metadata storage area and a determination is made as to whether the second data structure indicates that there are any new host writes. In response to determining that the second data structure indicates that there are new host writes, write access is secured to the metadata storage area, the first data structure is updated with contents of the second data structure to determine which additional storage locations need to be copied for formation of a next consistency group, and the second data structure is updated to indicate that that the second data structure is in an initialized state.

Abstract: In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

Abstract: A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information.

Abstract: A multi-level cache structure in accordance with one embodiment includes a first cache structure and a second cache structure. The second cache structure is hierarchically above the first cache. The second cache includes a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data. The selector array is configured to specify, for each corresponding tag entry, whether the data array includes the data corresponding to that tag entry.