Abstract: A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.

Abstract: An arithmetic processor of an embodiment comprises program counter, a program memory, registers, and a decoder. Also the arithmetic processor comprises an arithmetic unit that carries out an operation using the operand and operator acquired from the registers based on a decode result by the decoder, a data memory that stores constant data and an address in association with the data, and a load unit that comprises a load data address storing unit that stores a load data address indicating an address where the constant data is stored; and an increment unit that updates the load data address stored in the load data address storing unit. The load unit loads, from the data memory, constant data corresponding to an address specified by an operand of a load instruction from the decoder, and stores the constant data in a specific one of the registers.

Abstract: A queue management capability enables allocation and management of tracking queue entries, such as load and/or store queue entries, at execution time. By introducing execution-time allocation of load/store queue entries, the allocation point of those entries is delayed further into the execution stage of the instruction pipeline, reducing the overall time the entry remains allocated to a specific instruction. The queue management capability may also resolve deadlock conditions resulting from execution-time allocation of the queue entries and/or provide a mechanism to avoid such deadlock conditions.

Abstract: Embodiments relate to lightweight interrupts for floating point exceptions. An aspect includes, based on an exception occurring in a floating point unit of a processor during execution of an application, sending a lightweight interrupt corresponding to the exception to the application; and handling the exception by an exception handler of the application.

Abstract: Branch prediction in a computer processor, includes: fetching an instruction, the instruction comprising an address, the address comprising a first portion of a global history vector and a global history vector pointer; performing a first branch prediction in dependence upon the first portion of the global history vector; retrieving, in dependence upon the global history vector pointer, from a rolling global history vector buffer, a second portion of the global history vector; and performing a second branch prediction in dependence upon a combination of the first portion and second portion of the global history vector.

Abstract: A processor including physical registers, a reorder buffer, a master free list, a slave free list, a master recycle circuit, and a slave recycle circuit. The reorder buffer includes instruction entries in which each entry stores physical register indexes for recycling physical registers. The reorder buffer retires up to N instructions in each processor cycle. Each master and slave free list includes N input ports and stores physical register indexes, in which the master free list stores indexes of physical registers to be allocated to instructions being issued. When an instruction is retired, the master recycle circuit routes a first physical register index stored in an instruction entry of the instruction to an input port of the master free list, and the slave recycle circuit routes a second physical register index stored in the instruction entry of the instruction to an input port of the slave free list.

Abstract: A branch predictor for predicting branch instructions performs different branch prediction operations for branches executing in a transaction than those not-executing in a transaction, including suppressing branch prediction functions based on progress of a re-execution of a previously aborted transaction, the transaction buffering data and committing the buffered data to memory when the transaction completes, but discarding the buffered data when the transaction aborts.

Abstract: A processor includes an indicator configured to indicate a first mode or a second mode and a functional unit configured to perform computations with a full degree of accuracy when the indicator indicates the first mode and to perform computations with less than the full degree of accuracy when the indicator indicates the second mode.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: Systems, apparatuses, and methods for committing store instructions out of order from a store queue are described. A processor may store a first store instruction and a second store instruction in the store queue, wherein the first store instruction is older than the second store instruction. In response to determining the second store instruction is ready to commit to the memory hierarchy, the processor may allow the second store instruction to commit before the first store instruction, in response to determining that all store instructions in the store queue older than the second store instruction are non-speculative. However, if it is determined that at least one store instruction in the store queue older than the second store instruction is speculative, the processor may prevent the second store instruction from committing to the memory hierarchy before the first store instruction.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: A microprocessor implemented method for maintaining a guest return address stack in an out-of-order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native address space fetched during execution, the method also comprises performing the following: (a) pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein the GRAS is maintained at the fetch stage of the pipeline, and wherein the current entry comprises information regarding both a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS in response to processing a return instruction; and (c) fetching instructions from the native target return address in the current entry after the popping from the GRAS.

Abstract: A method of an aspect includes receiving a floating point rounding instruction. The floating point rounding instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point that each of the one or more floating point data elements are to be rounded to, and indicates a destination storage location. A result is stored in the destination storage location in response to the floating point rounding instruction. The result includes one or more rounded result floating point data elements. Each of the one or more rounded result floating point data elements includes one of the floating point data elements of the source, in a corresponding position, which has been rounded to the indicated number of fraction bits. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: Provided is a method for predicting a target address using a set of Indirect Target TAgged GEometric (ITTAGE) tables and a target address pattern table. A branch instruction that is to be executed may be identified. A first tag for the branch instruction may be determined. The first tag may be a unique identifier that corresponds to the branch instruction. Using the tag, the branch instruction may be determined to be in a target address pattern table, and an index may be generated. A predicted target address for the branch instruction may be determined using the generated index and the largest ITTAGE table. Instructions associated with the predicted target address may be fetched.

Abstract: A processor core supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The IDU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract: A method including fetching a group of instructions, including a group header for the group of instructions, where the group of instructions is configured to execute by a processor, and where the group header includes a field including locking information for at least one operand is provided. The method further includes storing a value of the at least one operand in at least one operand buffer of the processor and based on the locking information, locking a value of the at least one operand in the at least one operand of the buffer such that the at least one operand is not cleared from the at least one operand buffer of the processor in response to completing the execution of the group of instructions.

Abstract: A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor, is provided. The method further includes scheduling at least one of the group of instructions for execution by the processor before decoding the at least one of the group of instructions based at least on pre-computed ready state information associated with the at least one of the group of instructions.

Abstract: A method including fetching information regarding a group of instructions, where the group of instructions is configured to execute atomically by a processor, including an encoding format for the information regarding the group of instructions, is provided. The method further includes processing the encoding format to interpret the information regarding the group of instructions.

Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.