Abstract: A method for manufacturing a cooling circuit on at least one integrated circuit chip includes producing a cooling circuit on a first face of the chip. Producing the cooling circuit includes forming a definition pattern of the cooling circuit on the first face of the chip, the pattern having at least one layer of a sacrificial material; coating the pattern with at least one resin layer; and at least partially removing the sacrificial material from the pattern so as to open the cooling circuit.

Abstract: An organic light-emitting diode (OLED) display panel and a manufacture method thereof are provided, which can enable the organic material encapsulated inside to have the function of removing water and oxygen, thereby further ensuring a reliable lifespan of the OLED display panel.

Abstract: An integrated circuit having a plurality of field-effect transistors, wherein at least a proportion of the field-effect transistors implement a plurality of logic cells, a substrate, a well which is arranged in the substrate, and a supply circuit which is designed to connect the well to a supply potential, wherein the supply circuit is constituted by one or more field-effect transistors of the plurality of field-effect transistors.

Abstract: A semiconductor device includes a semiconductor element, a terminal electrode, and internal wiring. The semiconductor element is housed in a case. The terminal electrode is provided electrically connectable to an outside of the case. The internal wiring is provided in the case and electrically connects the semiconductor element and the terminal electrode. The internal wiring includes a fuse portion provided at a part of the internal wiring and configured to be melted by an overcurrent. The fuse portion includes a plurality of metal wires which are a group of parallel wires. Of the plurality of metal wires, a first metal wire is higher in resistance value than a second metal wire laid on an outer side relative to the first metal wire.

Abstract: A semiconductor device comprising at least a semiconductor component, a heat sink, a connecting element and an electrical circuit connected to the heat sink in an electrically conductive manner; wherein the semiconductor component and the heat sink are arranged at a distance from one another and are electrically and thermally conductively connected via the connecting element, wherein an electrical current can be supplied to the electrical circuit via the heat sink.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.

Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component which is embedded in the stack and a stabilizing structure arranged between a stack surface of the stack and a main surface of the component. The stabilizing structure provides an interface adhesion to the main surface of the component.

Abstract: The invention discloses a parallel electrode combination, which includes a first power module electrode and a second power module electrode, wherein a soldering portion of the first power module electrode and a soldering portion of the second power module electrode are respectively used to connect a copper layer of a power source inside a power module, and a connecting portion of the first power module electrode and a connecting portion of the second power module electrode are opposite in parallel. The invention further discloses a power module and a power module group using the parallel electrode combination. In the invention, the connecting portion of the first power module electrode and the connecting portion of the second power module electrode are opposite in parallel.

Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Abstract: The present technology relates to a solid-state image pickup element, electronic equipment, and a semiconductor apparatus that make it possible to reduce a surface reflection in an area in which a slit is formed and improve flare characteristics. A solid-state image pickup element includes a pixel area in which a plurality of pixels is two-dimensionally arranged in a matrix, a chip mounting area in which a chip is flip-chip mounted, and a dam area that is arranged around the chip mounting area and in which one or more slits that block an outflow of a resin are formed. In the dam area, the same OCL as that in the pixel area is formed. The present technology can be applied to a solid-state image pickup element etc. in which a chip is flip-chip mounted, for example.

Abstract: A base material includes one surface, and a side surface continuous with the one surface. Each of the one surface and the side surface has a sealed region to be sealed with mold resin. The one surface has a one surface rough region in the sealed region thereof. The side surface has a side surface rough region in the sealed region thereof.

Abstract: A display device includes a substrate including a pixel area and a peripheral area, a plurality of pixels disposed in the pixel area of the substrate, a first initialization line disposed in the peripheral area of the substrate, the first initialization line being configured to provide a first initialization voltage to the plurality of pixels, and a second initialization line disposed in the peripheral area of the substrate, the second initialization line being configured to provide a second initialization voltage to the plurality of pixels. At least a portion of the first initialization line may overlap with the second initialization line.

Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: An optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, an active layer disposed between the p-type semiconductor region and the n-type semiconductor region and formed as a multiple quantum well structure and having alternating quantum well layers and barrier layers, the quantum well layers emitting a first radiation in a first wavelength range, and at least one further quantum well layer disposed outside the multiple quantum well structure that emits a second radiation in a second wavelength range, wherein the first wavelength range is in an infrared spectral range invisible to a human eye, and the second wavelength range includes wavelengths at least partially visible to the human eye.

Abstract: A thermal dissipation structure for integrated circuits includes a semiconductor substrate, a thermal dissipation trench, a metal seed layer and a metal layer. The semiconductor substrate has a first surface and a second surface which is opposite to the first surface. Integrated circuits are located on and thermally coupled with the first surface. The thermal dissipation trench is formed within the second surface. The metal seed layer seals the thermal dissipation trench to define a thermal dissipation channel. The thermal dissipation channel includes an inlet and an outlet. The metal layer is an electroplated layer formed from the metal seed layer.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The method of manufacturing a display substrate includes manufacturing a plurality of gate insulation layers having different thicknesses on a base substrate in one patterning process.

Abstract: The present disclosure provides an OLED display motherboard and a method for manufacturing the same, a method for manufacturing the OLED display panel, and an OLED display device thereof. The OLED display motherboard includes a base substrate having a display region and a non-display region surrounding the display region, a TFT and an OLED device located within the display region of the base substrate, at least two crack stop slits located within the non-display region of the base substrate, an extending direction of the crack stop slit being the same as an extending direction of an edge of the display region of the base substrate, and adjacent crack stop slits being separated by a crack stop slit step, and an encapsulation layer covering the crack stop slit and the OLED device. A portion of the encapsulation layer has a non-uniform thickness.

Abstract: A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a first semiconductor die, a second semiconductor die, a bonding layer, and a through die via. The first semiconductor die includes a first semiconductor substrate and a first conductive pad exposed at an active surface of the first semiconductor die. The second semiconductor die includes a second semiconductor substrate and a second conductive pad exposed at an active surface of the second semiconductor die. The first semiconductor die is stacked over the second semiconductor die. The bonding layer is disposed between the first and the second semiconductor die. The through die via electrically connects the first semiconductor die and the second semiconductor die. The through die via is embedded in the first semiconductor substrate, penetrates through the first conductive pad and the bonding layer, and reaches the second conductive pad.