Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a channel fin over a substrate and forming a top spacer region around a top portion of the channel fin, wherein the top spacer region includes a dopant. A dopant drive-in process is applied, wherein the dopant drive-in process is configured to drive the dopant from the top spacer region into the top portion of the channel fin to create a doped top portion of the channel fin and a top junction between the doped top portion of the channel fin and a main body portion of the channel fin.
Type:
Grant
Filed:
June 28, 2018
Date of Patent:
February 1, 2022
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Abstract: A twistable light emitting diode display module including a twistable substrate, an electrode pattern layer, an insulating layer, a circuit layer, and a plurality of light emitting diode devices. The electrode pattern layer is disposed on the twistable substrate. The insulating layer is disposed on the electrode pattern layer, where an edge of the insulating layer has an opening, located at an edge of the twistable substrate and exposing a part of the electrode pattern layer. The circuit layer is disposed on the insulating layer and on sidewalls of the opening, and is connected to the electrode pattern layer. The plurality of light emitting diode devices are disposed on the circuit layer and are electrically connected to the circuit layer respectively, wherein each of the plurality of light emitting diode devices includes a driving circuit.
Type:
Grant
Filed:
March 9, 2020
Date of Patent:
December 21, 2021
Assignee:
National Taipei University of Technology
Abstract: A method of manufacturing a display panel includes preparing a work substrate that includes a mother substrate that has a plurality of cell areas, a light emitting element layer formed in each of the cell areas, and an encapsulation layer formed on each cell area, disposing a plurality of protective films in the cell areas, respectively, that cover the light emitting element layer and the encapsulation layer, cutting the work substrate along cutting lines at an outer side of the protective films of each cell area to form a preliminary display panel, grinding side surfaces of the preliminary display panel, and removing the protective films from each ground preliminary display panel to form the display panel.
Type:
Grant
Filed:
April 22, 2020
Date of Patent:
December 21, 2021
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Younghoon Lee, Youngji Kim, Yiseul Um, Wonje Jo, Young Seo Choi, Dongwon Han
Abstract: A thermosetting composition for use as an underfill material contains: a mono- or bifunctional acrylic compound; a thermo-radical polymerization initiator; silica; and an elastomer including a 1,2-vinyl group. The thermosetting composition is liquid and has a property of turning, when cured thermally, into a cured product having a relative dielectric constant of 3.2 or less at 25° C. and a dielectric loss tangent of 0.013 or less at 25° C.
Abstract: A method for fabricating an electronic package is provided. A plurality of packaging structures are provided, each of which having a carrier and at least one electronic component disposed on the carrier. The plurality of packaging structures are disposed on a supporting plate. An encapsulation layer is formed on the supporting plate and encapsulates the plurality of packaging structures. Even if there are various types of electronic packages of different specifications in the market, the molds that the encapsulation layer uses can still be developed for a supporting plate of a certain specification. Therefore, the fabrication cost of the electronic package is reduced.
Abstract: The present invention relates to a display apparatus using a semiconductor light emitting device and a manufacturing method therefor and, more specifically, to a display apparatus using a semiconductor light emitting device. The display apparatus according to the present invention comprises: a wiring board which comprises a wiring electrode; a conductive adhesive layer which covers the wiring electrode; and a plurality of semiconductor light emitting devices which are coupled to the conductive adhesive layer and are electrically connected to the wiring electrode, wherein the conductive adhesive layer is applied in a patterned form on each electrode of the semiconductor light emitting devices such that a plurality of adhesive regions are provided spaced apart from each other on the wiring board.
Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a peak portion positioned on the substrate, a gate insulating layer positioned on the peak portion and the substrate, a gate bottom conductive layer positioned on the gate insulating layer, and a first doped region positioned in the substrate and adjacent to one end of the gate insulating layer.
Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.
Type:
Grant
Filed:
October 30, 2019
Date of Patent:
November 16, 2021
Assignee:
SK hynix Inc.
Inventors:
Jee Won Chung, Dong Jin Kim, Byeung Ho Kim, Chang Hyun Kim
Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.
Type:
Grant
Filed:
April 22, 2020
Date of Patent:
November 9, 2021
Assignee:
GLOBALFOUNDRIES U.S. INC.
Inventors:
Vibhor Jain, Ajay Raman, Sebastian T. Ventrone, John J. Ellis-Monaghan, Siva P. Adusumilli, Yves T. Ngu
Abstract: Provided are a pixel structure, a mask, and a display device. The pixel structure includes a plurality of pixel groups arranged in an array. Each of the pixel groups includes a first pixel sub-group and a second pixel sub-group disposed adjacent to each other in a first direction. Each of the first pixel sub-group and the second pixel sub-group includes sub-pixels of three different colors, and each of the first pixel sub-group and the second pixel sub-group includes at least two sub-pixels having a same color and arranged consecutively.
Abstract: A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes, a semiconductor chip and a passive component are disposed on the connection structure in the one or more through-holes of the frame, a first encapsulant covers at least a portion of the passive component, and a second encapsulant covers at least a portion of the semiconductor chip. An upper surface of the second encapsulant is positioned at a level equal to or lower than an upper surface of the first encapsulant.
Abstract: A display apparatus includes a substrate comprising a display area and a non-display area. A light-emitting device is on the display area. A thin-film encapsulation layer is on the light-emitting device. The thin-film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. The organic encapsulation layer includes a plurality of organic particles having a core-shell structure that includes a hollow core and a shell surrounding the hollow core. A touch unit is on the thin-film encapsulation layer.
Type:
Grant
Filed:
April 24, 2020
Date of Patent:
October 26, 2021
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Younggu Kim, Jiyun Park, Jongmin Ok, Byoungduk Lee, Taekjoon Lee, Sunyoung Chang, Hyelim Jang, Baekkyun Jeon, Jinsoo Jung, Kyungseon Tak, Jaeheung Ha
Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
Type:
Grant
Filed:
March 20, 2020
Date of Patent:
October 26, 2021
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first FET, and a second FET formed over the substrate. The substrate has a first surface and a second surface, and the first surface and the second surface form a step. The first FET comprises a first gate dielectric layer over the first surface of the substrate. The second FET comprises a second gate dielectric layer thinner than the first gate dielectric layer over the second surface of the substrate.
Abstract: A method of manufacturing a display system includes forming a display element having a display active area over a silicon backplane, forming a display driver integrated circuit (DDIC), and bonding the display element to the display driver integrated circuit (DDIC). The display active area may include a light emitting diode such as an organic light emitting diode (OLED). Separately forming the display and the display circuitry may simplify formation of the OLED and allow for a higher density control interface between the display and the DDIC.
Type:
Grant
Filed:
July 31, 2019
Date of Patent:
October 26, 2021
Assignee:
Facebook Technologies, LLC
Inventors:
Min Hyuk Choi, Cheonghong Kim, Zhiming Zhuang
Abstract: The present invention concerns a power module comprising at least one power die, the at least one power die is embedded in a multilayer structure, the multilayer structure is an assembly of at least two sub-modules, each sub-module being formed of isolation and conductor layers and the power module further comprises at least one capacitor embedded in the multilayer structure for decoupling an electric power supply to the at least one power die embedded in the multilayer structure and at least one driving circuit of the at least one power die that is disposed on a surface of the multilayer structure or embedded completely or partially in the multilayer structure.
Type:
Grant
Filed:
April 5, 2017
Date of Patent:
October 19, 2021
Assignee:
MITSUBISHI ELECTRIC CORPORATION
Inventors:
Roberto Mrad, Stefan Mollov, Jeffrey Ewanchuk
Abstract: A method for manufacturing a cooling circuit on at least one integrated circuit chip includes producing a cooling circuit on a first face of the chip. Producing the cooling circuit includes forming a definition pattern of the cooling circuit on the first face of the chip, the pattern having at least one layer of a sacrificial material; coating the pattern with at least one resin layer; and at least partially removing the sacrificial material from the pattern so as to open the cooling circuit.
Type:
Grant
Filed:
November 6, 2019
Date of Patent:
October 19, 2021
Assignee:
Commissariat A L'Energie Atomique et aux Energies Alternatives
Abstract: An organic light-emitting diode (OLED) display panel and a manufacture method thereof are provided, which can enable the organic material encapsulated inside to have the function of removing water and oxygen, thereby further ensuring a reliable lifespan of the OLED display panel.
Type:
Grant
Filed:
May 13, 2019
Date of Patent:
October 19, 2021
Assignee:
Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
Inventors:
Yamei Bai, Jinchang Huang, Yu Gu, Jiajia Luo, Lin Yang, Xianjie Li