Patents Examined by Ajay K Arora
  • Patent number: 10276758
    Abstract: A two-stage singulation process is used in the fabrication of phosphor coated light emitting elements. Prior to the application of the phosphor coating, the individual light emitting elements are singulated using a laser dicing process (130); after application of the phosphor coating (150), the phosphor coated light emitting elements are singulated using a mechanical dicing process (180). Before laser dicing of the light emitting elements, the wafer is positioned on a piece of dicing- or die-attach-tape held by a frame; after laser dicing, the tape is stretched (140) to provide space between the individual light emitting elements that allows for the wider kerf width of the subsequent mechanical dicing (180) after application of the phosphor coating (150).
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 30, 2019
    Assignee: Lumileds LLC
    Inventor: Frank Lili Wei
  • Patent number: 10269979
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Masahiro Takahashi
  • Patent number: 10263024
    Abstract: The present technology relates to an imaging element, an electronic device, and a manufacturing method that make it possible to prevent color mixing in a pixel adjacent to a phase difference detection pixel and to make the light receiving sensitivity high or more. An anti-reflection film is formed only on the side wall of a light blocking unit that blocks part of the incident light on a photo diode of phase difference detection pixels for detecting the phase difference out of a plurality of pixels. Thereby, the light reflected at the side wall of the light blocking unit does not enter a photo diode of an adjacent pixel, and therefore color mixing is prevented. Furthermore, since the anti-reflection film is not formed on an interlayer layer, the light receiving sensitivity of the light that directly enters the photo diode is not reduced. The present technology can be applied to imaging elements.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: April 16, 2019
    Assignee: Sony Corporation
    Inventor: Masashi Nakata
  • Patent number: 10247881
    Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 2, 2019
    Inventor: John H. Zhang
  • Patent number: 10224234
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: March 5, 2019
    Assignee: Sony Corporation
    Inventor: Masaki Okamoto
  • Patent number: 10217801
    Abstract: A light-emitting structure, a display device and a light source device are disclosed; the light-emitting structure comprises a first light-emitting component (10) and a second light-emitting component (20). The first light-emitting component (10) comprises a first light-emitting layer (12) and a second light-emitting layer (14) and the second light-emitting component (20) comprises a third light-emitting layer (22). A combination of electrical connection of the first light-emitting component (10) and the second light-emitting component (14) is driven by AC current as a whole; the first light-emitting layer (12) and the second light-emitting layer (14) do not emit light at the same time; the third light-emitting layer (22) emits light at the same time either with the first light-emitting layer (12) or the second light-emitting layer (14). AC drive is adopted in the light-emitting structure and is easy to achieve adjustment of color and illumination intensity.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 26, 2019
    Inventors: Guang Yan, Chang Yen Wu
  • Patent number: 10204973
    Abstract: A display device includes a pixel circuit that includes a thin-film transistor. The thin-film transistor includes a gate electrode, a semiconductor layer formed above the gate electrode, a gate insulating layer formed between the gate electrode and the semiconductor layer, a channel protective layer formed on the semiconductor layer, and a source electrode and a drain electrode that are formed above the channel protective layer and electrically connected to the semiconductor layer. The source electrode and the drain electrode are formed in different layers.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 12, 2019
    Assignee: JOLED INC.
    Inventor: Shinya Ono
  • Patent number: 10205094
    Abstract: A raw material solution (6), in which an organic semiconductor material is dissolved in a solvent, is supplied to a substrate (1). The solvent is evaporated so that crystals of the organic semiconductor material are precipitated. Thus, an organic semiconductor thin film (7) is formed on the substrate (1). An edge forming member (2) having a contact face (2a) on one side is used and located opposite the substrate (1) so that the plane of the contact face (2a) intersects the surface of the substrate (1) at a predetermined angle. The raw material solution (6) is supplied to the substrate (1) and formed into a droplet (6a) that comes into contact with the contact face (2a).
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 12, 2019
    Assignee: PI-CRYSTAL INC.
    Inventors: Junichi Takeya, Junshi Soeda
  • Patent number: 10199504
    Abstract: Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 5, 2019
    Inventors: Zhengliang Li, Qi Yao, Zhanfeng Cao, Bin Zhang, Xiaolong He, Jincheng Gao, Xiangchun Kong, Wei Zhang
  • Patent number: 10199574
    Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 5, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Patent number: 10199392
    Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 5, 2019
    Inventors: Ronald K. Sampson, Nicolas Loubet
  • Patent number: 10186557
    Abstract: An OLED display device and a manufacturing method thereof, a display device and a vaporization mask are disclosed. Five sub-pixels (101) in a pixel unit (10) of the display device includes at least one red, at least one green and at least one blue sub-pixel. Four of the five sub-pixels (101) are distributed at four corners and have the same shape and size, the other one is surrounded by the four sub-pixels (101), and the four sub-pixels (101) and the one sub-pixel (101) are of different colors. Any one sub-pixel (101) at a corner of the pixel unit (10) forms a regular pattern with one sub-pixel at a corner in each of other three adjacent pixel units (10), and in the regular pattern, all of the sub-pixels are of a same color and each occupies ΒΌ of the pattern. The display device can reduce the difficulty of manufacturing vaporization openings of a mask and increase the display resolution.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 22, 2019
    Inventor: Lifei Ma
  • Patent number: 10186683
    Abstract: A flexible OLED display panel includes: a flexible substrate; an OLED device disposed on the flexible substrate; a first encapsulation layer disposed on the flexible substrate and covering the OLED device; a bank layer disposed on the flexible substrate and surrounding a periphery of the first encapsulation layer, the bank layer including a plurality of noncontinuous bank units that are disposed in a chain form; and a second encapsulation layer disposed on the flexible substrate and covering the first encapsulation layer and the bank layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 22, 2019
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Huan Jiang, Hsin-Ju Ho
  • Patent number: 10186690
    Abstract: Provided is an organic EL display panel manufacturing method. The organic EL display panel includes a plurality of semiconductor elements. The method includes: forming, on a planarization film formed above the semiconductor elements, lower electrodes in one-to-one correspondence with the pixels; forming an organic layer including a light-emitting layer on the lower electrodes; forming an upper electrode on the organic layer; detecting any of the lower electrodes that includes a defect; and forming, on the planarization film or any of the lower electrodes that includes a defect, a protrusion for connecting the lower electrode and the upper electrode.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 22, 2019
    Assignee: JOLED INC.
    Inventors: Toshiaki Onimaru, Tetsuro Kondo
  • Patent number: 10181516
    Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 15, 2019
    Inventors: Luigi Colombo, Archana Venugopal
  • Patent number: 10180587
    Abstract: A light modulator may include: a light modulating unit formed as a pixel-array type by using a PIN diode including multiple quantum wells including a Group-III nitride semiconductor material, and configured to modulate light by electroabsorption; and/or a control unit including a transistor configured to control voltage applied to the PIN diode of the light modulating unit. The PIN diode and the transistor may be arrayed in an active matrix form.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duhyun Lee, Byungkyu Lee
  • Patent number: 10170445
    Abstract: A method for electrically coupling a pad and a front face of a pillar, including shaping the front face pillar, the front face having at least partially a convex surface, applying a suspension to the front face or to the pad, wherein the suspension includes a carrier fluid, electrically conducting microparticles and electrically conducting nanoparticles, arranging the front face of the pillar opposite to the pad at a distance such that the carrier fluid bridges at least partially a gap between the front face of the pillar and the pad, evaporating the carrier fluid thereby confining the microparticles and the nanoparticles, and thereby arranging the nanoparticles and the microparticles as percolation paths between the front face of the pillar and the pad, and sintering the arranged nanoparticles for forming metallic bonds at least between the nanoparticles and/or between the nanoparticles and the front face of the pillar or the pad.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 1, 2019
    Inventors: Thomas J. Brunschwiler, Richard Dixon, Maaike M. Visser Taklo, Bernhard Wunderle, Kerry Yu, Jonas Zuercher
  • Patent number: 10153328
    Abstract: The present invention is to provide an Organic Light-Emitting Diode (OLED) display panel and a package method thereof. The method includes forming simultaneously a supporter and a hydrophobic wall on an outer position of and enclosing the OLED device by screen printing, wherein the hydrophobic wall is on an outer position of the supporter; and bonding the cover plate and the OLED substrate. The present invention can effectively protect the OLED device from outer moisture and oxygen to improve package effect and increase life of the OLED device. The supporter and the hydrophobic wall are formed simultaneously by screen printing so the method is simple and the manufacturing efficiency is improved.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: December 11, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Wei Yu
  • Patent number: 10147771
    Abstract: An organic light emitting diode display includes a red pixel including a red organic emission layer, a blue pixel including a blue organic emission layer, a green pixel including a green organic emission layer, a main spacer adjacent to the blue pixel, and a sub spacer shorter than the main spacer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 4, 2018
    Inventor: Sun-Kyo Jung
  • Patent number: 10141358
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 27, 2018
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng