Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: The present invention discloses a pixel unit and a method for manufacturing the same, a display panel, and a display apparatus. A pixel unit comprises a first electrode, a pixel defining layer, a light emitting layer and a second electrode, wherein the second electrode comprises a first portion and a second portion; the pixel defining layer defines a pixel region, the light emitting layer and the first portion of the second electrode are disposed successively within the pixel region, and an upper surface of the first portion of the second electrode is substantially in same plane with an upper surface of the pixel defining layer; and, the second portion of the second electrode is positioned over the first portion and is connected with a second electrode of an adjacent pixel unit.

Abstract: A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.

Abstract: Provided is a transparent electrode having both sufficient conductivity and light transmittance, and also provided is an electronic device which improves performance by using said transparent electrode. Further provided is method of manufacturing said transparent electrode. This transparent electrode is provided with a nitrogen-containing layer and an electrode layer. The nitrogen-containing layer is formed at a deposition speed of 0.3 nm/s or greater, and is configured using a compound containing nitrogen atoms. Further, the electrode layer is provided adjacent to the nitrogen-containing layer, has a 12 nm or lower film thickness and a measurable sheet resistance, and is configured using silver or an alloy having silver as the main component.

Abstract: The invention provides a thioxanthone aromatic amine compound and an organic light emitting device using the compound. The thioxanthone aromatic amine compound includes a compound expressed by formula (I) or formula (II): where Ar1 and Ar2 each are selected from ammonia compounds with structures respectively expressed by formula (III) to formula (VII), or hydrogen atom, thioxanthone aromatic amine compound of the invention has single structure, determinate molecular weight, and has better solubility and film-forming property, and also has low biochemical temperature and decomposition temperature, and stable film morphology.

Abstract: A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.

Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: According to one embodiment, a display device includes a first substrate including a first insulative substrate, an outer peripheral wiring formed above the first insulative substrate, an insulation film disposed on the outer peripheral wiring, a pixel electrode formed on the insulation film in an active area for displaying an image, and a first bank formed in a line shape on the insulation film in a peripheral area surrounding the active area, a second substrate including at least a second insulative substrate, and a sealant which is provided in a manner to envelop the first bank, and which attaches the first substrate and the second substrate.

Abstract: Provided are a pressure-sensitive adhesive film and a method of manufacturing an organic electronic device using the same. The pressure-sensitive adhesive film that may effectively block moisture or oxygen penetrated into an organic electronic device from an external environment, and exhibit reliability under harsh conditions such as high temperature and high humidity and excellent optical characteristics is provided.

Abstract: A window for a display device and a display device including the same are provided. The window for the display device includes: a window substrate having a first groove in a display area transmitting an image and a second groove in a non-display area adjacent to the display area; a polarizing film in the first groove; and a printed layer in the second groove.

Abstract: A combination switch includes an Insulated Gate Bipolar Transistor (IGBT), an anti-parallel diode, and a saturable inductor. The diode and inductor are coupled in series between a collector and an emitter of the IGBT. The inductor is fashioned so that it will come out of saturation when a forward bias current flow through the diode falls below a saturation current level. When the diode current falls (for example, due to another combination switch of a phase leg turning on), the diode current initially falls at a high rate until the inductor current drops to the saturation current level. Thereafter, the diode current falls at a lower rate. The lower rate allows the diode current to have a soft landing to zero current, thereby eliminating or reducing voltage and/or current spikes that would otherwise occur. Multiple methods of implementing and manufacturing the saturable inductor are disclosed.

Abstract: A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surface layer of the barrier layer, in which resistance is kept lower than portions around by containing impurity; a source electrode and a drain electrode connected to the barrier layer at positions sandwiching the low-resistance region; agate insulating layer provided on the low-resistance region; and a gate electrode provided above the low-resistance region through the gate insulating layer.

Abstract: A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a second aperture that includes a bottom portion of the first aperture and is formed on a common electrode, a third aperture that includes at least a part of the bottom portion of the first aperture, is included in a second aperture and is formed on a third interlayer insulating film, and a fourth aperture that is formed on the first interlayer insulating film in a region where the third aperture overlaps with the bottom portion of the first aperture.

Abstract: A sealed structure with high sealing capability, in which a pair of substrates is attached to each other with a glass layer is provided. The sealed structure has a first and second substrates, a first surface of the first substrate facing a first surface of the second substrate, and the glass layer which is in contact with the first and second substrates, defines a space between the first and second substrates, and is provided along the periphery of the first surface of the first substrate. The first substrate has a corner portion. The area of the first surface of the first substrate is smaller than or equal to that of the first surface of the second substrate. In at least one of respective welded regions between the glass layer and the first or second substrate, the width of the corner portion is larger than that of the side portion.

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

Abstract: A system and method employing at least one semiconductor device, or an arrangement of insulating and metal layers, having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid strand proximate to the detecting region, and a method for manufacturing such a semiconductor device. The system and method can thus be used for sequencing individual nucleotides or bases of ribonucleic acid (RNA) or deoxyribonucleic acid (DNA). The semiconductor device includes at least two doped regions, such as two n-typed regions implanted in a p-typed semiconductor layer or two p-typed regions implanted in an n-typed semiconductor layer. The detecting region permits a current to pass between the two doped regions in response to the presence of the component of the polymer, such as a base of a DNA or RNA strand.

Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

Abstract: Disclosed is an OLED display panel, a method for manufacturing the same, and a display apparatus. The OLED display panel comprises a substrate and a light emitting structure including a plurality of sets of light emitting units sequentially arranged on the substrate side by side, each set of light emitting units including a first light emitting unit, a second light emitting unit and a third light emitting unit. In each set of light emitting units, at least two of the first, second and third light emitting units are located in different layers. The OLED display panel and the display apparatus can reduce signal attenuation and crosstalk between different signals.

Abstract: A semiconductor device includes a substrate, an active layer, a transistor, and a capacitor. The active layer is disposed on the substrate, and the active layer is divided into a first portion and a second portion. The transistor and the capacitor are disposed on the substrate. The transistor includes the second portion, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively and electrically connected to the second portion. The gate electrode is disposed on the second portion. The capacitor includes the first portion, a first electrode, a first insulating layer, and a second electrode. The first electrode is electrically connected to the first portion and the source electrode. The first insulating layer is disposed on the first portion. The second electrode is disposed on the first insulating layer and is electrically connected to the gate electrode.

Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.