Patents Examined by Ajay Ojha
  • Patent number: 11984155
    Abstract: Methods, systems, and devices for a differential write operation are described. The operations described herein may be used to alter a portion of a program file from a first state to a second state. For example, a file (e.g., a patch file) that is associated with a signature may be received at a memory device. Based on an authentication process, the file may be used to alter the program file to the second state. In some examples, the program file may be altered to the second state using a buffer of the memory device. A host system may transmit a file that includes the difference between the first state and the second state. A signature may be associated with the file and may be used to authenticate the file.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Olivier Duval
  • Patent number: 11984172
    Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Patent number: 11983606
    Abstract: Disclosed are a method and device for constructing a quantum circuit of a QRAM architecture, the QRAM architecture being configured for accessing data and being a binary tree structure, the method including: partitioning the binary tree structure into basic circuit structures, wherein a basic circuit structure comprises address bits and data bits of one subtree node and data bits of two child nodes in the lower layer of the one subtree node; determining qubits required for a basic quantum circuit to be constructed, according to qubits included in the basic circuit structure; determining an input and an output of the basic quantum circuit to be constructed, according to action relationships between the qubits required for the basic quantum circuit to be constructed; and constructing a basic quantum circuit corresponding to the basic circuit structure, according to the input and the output using the required qubits and quantum logic gates.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: May 14, 2024
    Assignee: Origin Quantum Computing Technology (Hefei) Co., Ltd.
    Inventors: Ye Li, Ningbo An, Menghan Dou
  • Patent number: 11972827
    Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 30, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Fujimi Kaneko, Makoto Senoo, Takamichi Kasai
  • Patent number: 11967366
    Abstract: A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: NUMEM INC.
    Inventor: Bindiganavale S. Nataraj
  • Patent number: 11967378
    Abstract: The application discloses an analog content addressable memory (CAM) device, an analog CAM cell and a method for data searching and comparing thereof. The CAM cell includes: a first memory cell and a second memory cell coupled to each other, wherein the analog CAM cell stores analog storage data which is corresponding to a match range, the match range is determined based on first and second threshold voltages of the analog CAM cell; an analog search data is converted into first and second analog search voltages; the first and the second memory cells receive the first and the second analog search voltages; and the analog CAM memory cell generates a memory cell current, or the analog CAM memory cell keeps or discharges a match line voltage on a match line coupled to the analog CAM memory cell.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Po-Hao Tseng
  • Patent number: 11961570
    Abstract: In one aspect, a method for NOR flash cell-array programming in a neural circuit includes the step of erasing a cell array. The method includes the step of programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref). The method includes the step of generating, with the reference cells, a current or voltage, reference signal. The method includes the step of using the reference signal to bias the neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell). The method includes the step of programming a set of neural cells of a neural cell array to their respective target threshold voltages.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 16, 2024
    Inventors: Vishal Sarin, Vikram Kowshik, Purval Sule, Siraj Fulum Mossa
  • Patent number: 11961559
    Abstract: A storage device includes a nonvolatile memory device and a memory controller allowing the nonvolatile memory device to perform a read operation on memory cells belonging to a selected page in a selected memory block. After the read operation, the memory controller allows the nonvolatile memory device to perform a first check read operation on memory cells of a first neighbor page while sequentially selecting sets of read voltages. After the first check read operation, the memory controller allows the nonvolatile memory device to perform a second check read operation on memory cells of a second neighbor page while sequentially selecting the sets of read voltages. In the second check read operation, the memory controller first selects a set of read voltages, which are used in the first check read operation in which error correction succeeds.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunjung Lee, Hee-Woong Kang
  • Patent number: 11961008
    Abstract: Methods for controlled segregation of blocks of information encoded in the sequence of a biopolymer, such as nucleic acids and polypeptides, with rapid retrieval based on multiply addressing nanostructured data have been developed. In some embodiments, sequence controlled polymer memory objects include data-encoded biopolymers of any length or form encapsulated by natural or synthetic polymers and including one or more address tags. The sequence address labels are used to associate or select memory objects for sequencing read-out, enabling organization and access of distinct memory objects or subsets of memory objects using Boolean logic. In some embodiments, a memory object is a single-stranded nucleic acid scaffold strand encoding bit stream information that is folded into a nucleic acid nanostructure of arbitrary geometry, including one or more sequence address labels. Methods for controlled degradation of biopolymer-encoded blocks of information in the memory objects are also developed.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: April 16, 2024
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Mark Bathe, Sakul Ratanalert, Remi Veneziano, James Banal, Tyson Shepherd
  • Patent number: 11957071
    Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yukio Hayakawa, Jooheon Kang, Myunghun Woo, Gunwook Yoon, Doohee Hwang
  • Patent number: 11954587
    Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.
    Type: Grant
    Filed: September 25, 2023
    Date of Patent: April 9, 2024
    Assignee: DEEPX CO., LTD.
    Inventors: Seong Jin Lee, Jin Gun Song, Lok Won Kim
  • Patent number: 11948965
    Abstract: An uneven-trench pixel cell includes a semiconductor substrate that includes a floating diffusion region, a photodiode region, and, between a front surface and a back surface: a first sidewall surface, a shallow bottom surface, a second sidewall surface, and a deep bottom surface. The first sidewall surface and a shallow bottom surface define a shallow trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A shallow depth of the shallow trench exceeds a junction depth of the floating diffusion region. The second sidewall surface and a deep bottom surface define a deep trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A distance between the deep bottom surface and the front surface defines a deep depth, of the deep trench, that exceeds the shallow depth.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 2, 2024
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11948658
    Abstract: An accumulator includes an accumulating adder configured to add input data and latch data to output accumulation data, a selector configured to receive external data and the accumulation data, and output one of the external data and the accumulation data as selection data, and a latch circuit configured to latch the selection data output from the selector to transmit latched selection data into the accumulating adder as the latch data.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Joon Hong Park
  • Patent number: 11942152
    Abstract: There are increasing needs of searching on which data in a storage circuit is most similar to input information from the outside. Expectations for storage circuits having such memory techniques are high, and to enable a computer to handle information from the outside more flexibly is considered an essential technique. To achieve such techniques, a storage circuit needs to have a function of measuring a degree of similarity between stored data and input data. In an approximate-search-circuit, a memory matrix of a conventional storage circuit is caused to function as a data conversion circuit for calculating the inner-product distance between stored data and input data, by inputting the input data to the memory matrix in the form of a time series of pulse-signals, and the location of stored data with the highest inner-product is output from a circuit that calculates the inner-product in real time.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 26, 2024
    Inventor: Yoshinori Okajima
  • Patent number: 11942135
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Jaime Cummins
  • Patent number: 11935594
    Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 19, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
  • Patent number: 11915787
    Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Feng Young, Yu-Ming Lin, Shih-Lien Linus Lu, Han-Jong Chia, Sai-Hooi Yeong, Chia-En Huang, Yih Wang
  • Patent number: 11917824
    Abstract: A semiconductor storage device of an embodiment includes: a plurality of columnar bodies that penetrate a predetermined film; and a beam that reaches a predetermined depth of the predetermined film shallower than depths of the plurality of columnar bodies and couples the plurality of columnar bodies together with a width smaller than widths of the plurality of columnar bodies.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventor: Takahiro Adachi
  • Patent number: 11908544
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 20, 2024
    Inventor: Kang-Yong Kim
  • Patent number: 11907830
    Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer. A plurality of convolution engines each perform a convolution operation by applying a filter to a data window. Each of the plurality of convolution engines includes multiplication logic that combines a weight of a filter with a respective data value of a data window; control logic that receives configuration information identifying a set of filters for operation on a set of data windows at the plurality of convolution engines; determines a sequence of convolution operations for evaluation at the multiplication logic; requests weights and data values for at least partially applying a filter to a data window; and causes the multiplication logic to combine the weights with their respective data values. Accumulation logic accumulates the results of a plurality of combinations performed by the multiplication logic to form an output for a convolution operation of the determined sequence.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: February 20, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Christopher Martin