Patents Examined by Ajay Ojha
  • Patent number: 10971221
    Abstract: Aspect for storage device with fault tolerance capability for neural networks are described herein. The aspects may include a first storage unit of a storage device. The first storage unit is configured to store one or more first bits of data and the data includes floating point type data and fixed point type data. The first bits include one or more sign bits of the floating point type data and the fixed point type data. The aspect may further include a second storage unit of the storage device. The second storage unit may be configured to store one or more second bits of the data. In some examples, the first storage unit may include an ECC memory and the second storage unit may include a non-ECC memory. The ECC memory may include an ECC check Dynamic Random Access Memory and an ECC check Static Random Access Memory.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 6, 2021
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Shaoli Liu, Xuda Zhou, Zidong Du, Daofu Liu
  • Patent number: 10971238
    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Inventors: Kohji Kanamori, Yongseok Kim, Kyunghwan Lee, Junhee Lim
  • Patent number: 10965317
    Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 30, 2021
    Assignee: IP Reservoir, LLC
    Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
  • Patent number: 10963793
    Abstract: Solution of a problem of determining values of a set of N problem variables xi makes use of a quantum processor that has a limited number of hardware elements for representing quantum bits and/or limitations on coupling between quantum bits. A method includes accepting a specification of the problem that includes a specification of a set of terms where each term corresponds to a product of at least three variables and is associated with a non-zero coefficient. A set of ancilla variables, each ancilla variable corresponding to a pair of problem variables, is determined by applying an optimization procedure to the specification of the set of the terms. The accepted problem specification is then transformed according to the determined ancilla variables to form a modified problem specification for use in configuring the quantum processor and solution of problem.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: March 30, 2021
    Assignee: President and Fellows of Harvard College
    Inventors: Alan Aspuru-Guzik, Ryan Babbush, Bryan O'Gorman
  • Patent number: 10957372
    Abstract: A fixed magnetic skyrmion in a memory or Boolean logic or non-Boolean computing element is reversibly switched or switchable (1) with only an electric field and without a magnetic field or spin current; and (2) using voltage control of magnetic anisotropy (VCMA) to reduce the spin current needed to switch the skyrmion. Some embodiments switch between four states: two skyrmion states and two ferromagnetic states. Other embodiments switch between two states which are both skyrmionic, in which case the switching process may use ferromagnetic intermediate states, or both ferromagnetic, in which case the switching process may use skyrmionic intermediate states, or between a Skyrmion and ferromagnetic state. Boolean and non-Boolean logic devices are also provided which are based on these switching methods.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: March 23, 2021
    Assignee: VIRGINIA COMMONWEALTH UNIVERSITY
    Inventors: Jayasimha Atulasimha, Dhritiman Bhattcaharya, Md Mamun Al-Rashid
  • Patent number: 10957396
    Abstract: Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 23, 2021
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jong-Ho Lee, Sung-Tae Lee
  • Patent number: 10957369
    Abstract: Systems and memory devices that include a transistor shared by word line drivers are described. A memory device includes a first word line driver coupled to a first word line, and a second word line driver coupled to a second word line. The memory device also includes a transistor comprising a first terminal coupled to an output of the first word line driver, and a second terminal coupled to an output of the second word line driver.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tae H Kim
  • Patent number: 10943653
    Abstract: A receiver circuit is configured to receive input signals having a first reference voltage level. The first reference voltage level is a first logical high voltage level. The receiver circuit comprises an input stage comprising a resistive voltage divider. The resistive voltage divider is configured to convert the input signals having the first reference voltage level to input signals having a second reference voltage level. The second reference voltage level is a second logical high voltage level. The receiver circuit comprises a preamplifier configured to receive and amplify the input signals having the second reference voltage level.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventor: Marcel A. Kossel
  • Patent number: 10943632
    Abstract: A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hironobu Furuhashi
  • Patent number: 10943625
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Patent number: 10937478
    Abstract: An apparatus includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a second MTJ having a second magnetic characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first MTJ. The second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second MTJ, The apparatus further includes a metallic separator coupling the first MTJ with the second MTJ, wherein the first MTJ and the second MTJ are arranged in series.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 2, 2021
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Marcin Gajek, Mourad El Baraji, Eric Michael Ryan
  • Patent number: 10937511
    Abstract: A method of operating a controller that controls an operation of a semiconductor memory device includes controlling the semiconductor memory device to perform an operation for a selected memory block, determining whether or not the operation is successful, and compensating for a change in a threshold voltage distribution of select transistors by changing an operation voltage applied to the select transistors included in the selected memory block, based on whether or not the operation is successful.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Ho Her, Dong Hyun Kim, Seung Il Kim, Youn Ho Jung
  • Patent number: 10930330
    Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jun Shin, Tae-Young Oh
  • Patent number: 10930632
    Abstract: A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command/address signals from one of the RCD and the controller to the first plurality of volatile memories.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: William A. Lendvay
  • Patent number: 10922000
    Abstract: A controller, an operating method thereof and a memory system including the same are disclosed. The operating method of a controller which controls a memory system including a nonvolatile memory device including a plurality of data storage regions, includes receiving a command from a host, determining whether a pre-condition command is included in the command by confirming whether the received command has a reserved area, and switching the memory system to a pre-condition state by performing a secure erase and patterning on the nonvolatile memory device according to the pre-condition command included in the command.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Do Hyun Kim
  • Patent number: 10923172
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Johnson, Christopher G. Wieduwilt, Daniel S. Miller, Yoshinori S. Fujiwara
  • Patent number: 10923211
    Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method generates a pseudorandom sequence and combines the first encoded data with the pseudorandom sequence to produce second encoded data. In this configuration, the first encoded data is scrambled based on the starting seed while, based on combining the first encoded data with the pseudorandom sequence, the second encoded data is scrambled based on the destination seed. Thereafter, the second encoded data is stored in the second location.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: February 16, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Robert B. Eisenhuth
  • Patent number: 10923186
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: February 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
  • Patent number: 10916553
    Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a pillar including a length, a memory cell string and control lines located along a first segment of the pillar, and select lines located along a second segment of the pillar. The control lines include at least a first control line and a second control line. The first control line is adjacent the second control line. The first control line is separated from the second control line by a first distance in a direction of the length of the pillar. The select lines include at least a first select line and a second select line. The first select line is separated from the second select line by a second distance in the direction of the length of the pillar. The second distance is less than the first distance.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 10910080
    Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bae Bang, Seung Hwan Song, Dae Seok Byeon, Il Han Park, Hyun Jun Yoon, Han Jun Lee, Na Young Choi