Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.

Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

Abstract: A topological spin memory effect, defined as the recovery of magnetic skyrmions or magnetic bubble skyrmions in magnetic thin films after a transition to a dramatically different spin texture, is used for encrypted non-volatile information storage. The storage strategy is based on magnetic skyrmions, that is, topologically protected spin textures comprising chiral domain walls surrounding small (e.g., nanometers to microns in diameter), typically circular, single-domain cores. Systems and methods are described for encrypted non-volatile information storage based on a spin memory effect in magnetic thin films that support skyrmions. Systems and methods encrypt and recover information stored in the form of magnetic skyrmions.

Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

Abstract: A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

Abstract: A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.

Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

Abstract: The disclosure describes various aspects of optical control of atomic quantum bits (qubits) for phase control operations. More specifically, the disclosure describes methods for coherently controlling quantum phases on atomic qubits mediated by optical control fields, applying to quantum logic gates, and generalized interactions between qubits. Various attributes and settings of optical/qubit interactions (e.g., atomic energy structure, laser beam geometry, polarization, spectrum, phase, background magnetic field) are identified for imprinting and storing phase in qubits. The disclosure further describes how these control attributes are best matched in order to control and stabilize qubit interactions and allow extended phase-stable quantum gate sequences.

Abstract: A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.

Abstract: The present disclosure relates to systems, methods, and computer readable media for implementing fault isolation in memory without incurring a die size penalty. For example, systems disclosed herein may involve identifying row addresses for sub-word line drivers accessing data from a memory block (e.g., a dynamic random-access memory (DRAM) block of memory). The systems disclosed herein may further serialize or otherwise compile bit rows into a prefetch bit including a pattern of bits. In generating the prefetch bit, the systems described herein may selectively group bits of data into respective regions that enable an error correction scheme to be applied to the pattern of data while minimizing a likelihood of uncorrectable errors within the prefetch bit.

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

Abstract: Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: A semiconductor system includes a first semiconductor device configured to output a clock and pattern data, configured to receive a strobe signal and output data, and configured to adjust a duty ratio of the strobe signal by comparing odd data and even data that are generated from the output data and the pattern data, in synchronization with the strobe signal and a second semiconductor device configured to store the pattern data in synchronization with the clock, configured to output the clock as the strobe signal by adjusting a duty ratio of the clock, and configured to output the stored pattern data as the output data.

Abstract: A content addressable memory (CAM) device includes first to third CAM circuits and first to second peripheral circuits. The first CAM circuit stores a first bit of a first word. The second CAM circuit is arranged adjacent to the first CAM circuit and stores a first bit of a second word. The third CAM circuit is arranged adjacent to the second CAM circuit and store a second bit of the second word. The first to the third CAM circuits are arranged in a memory row. The first peripheral circuit accesses the first bits in the first and the second words. The second peripheral circuit accesses the second bit of the second word.

Abstract: Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory array can include a serialization circuit configured to convert parallel data streams of read data received from separately switched memory banks into a single, serialized, read data stream in a burst read mode. The memory array can also include a de-serialization circuit configured to convert a received, serialized write data stream on an input bus for a write operation into separate, parallel write data streams to be written simultaneously to the memory banks in a burst write mode.

Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

Abstract: A memory system having a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device) on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the first data and writing of the second data are performed in parallel.