Abstract: A storage device includes a nonvolatile memory device and a memory controller allowing the nonvolatile memory device to perform a read operation on memory cells belonging to a selected page in a selected memory block. After the read operation, the memory controller allows the nonvolatile memory device to perform a first check read operation on memory cells of a first neighbor page while sequentially selecting sets of read voltages. After the first check read operation, the memory controller allows the nonvolatile memory device to perform a second check read operation on memory cells of a second neighbor page while sequentially selecting the sets of read voltages. In the second check read operation, the memory controller first selects a set of read voltages, which are used in the first check read operation in which error correction succeeds.

Abstract: Methods for controlled segregation of blocks of information encoded in the sequence of a biopolymer, such as nucleic acids and polypeptides, with rapid retrieval based on multiply addressing nanostructured data have been developed. In some embodiments, sequence controlled polymer memory objects include data-encoded biopolymers of any length or form encapsulated by natural or synthetic polymers and including one or more address tags. The sequence address labels are used to associate or select memory objects for sequencing read-out, enabling organization and access of distinct memory objects or subsets of memory objects using Boolean logic. In some embodiments, a memory object is a single-stranded nucleic acid scaffold strand encoding bit stream information that is folded into a nucleic acid nanostructure of arbitrary geometry, including one or more sequence address labels. Methods for controlled degradation of biopolymer-encoded blocks of information in the memory objects are also developed.

Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

Abstract: An accumulator includes an accumulating adder configured to add input data and latch data to output accumulation data, a selector configured to receive external data and the accumulation data, and output one of the external data and the accumulation data as selection data, and a latch circuit configured to latch the selection data output from the selector to transmit latched selection data into the accumulating adder as the latch data.

Abstract: An uneven-trench pixel cell includes a semiconductor substrate that includes a floating diffusion region, a photodiode region, and, between a front surface and a back surface: a first sidewall surface, a shallow bottom surface, a second sidewall surface, and a deep bottom surface. The first sidewall surface and a shallow bottom surface define a shallow trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A shallow depth of the shallow trench exceeds a junction depth of the floating diffusion region. The second sidewall surface and a deep bottom surface define a deep trench, located between the floating diffusion region and the photodiode region, that extends into the semiconductor substrate from the front surface. A distance between the deep bottom surface and the front surface defines a deep depth, of the deep trench, that exceeds the shallow depth.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

Abstract: There are increasing needs of searching on which data in a storage circuit is most similar to input information from the outside. Expectations for storage circuits having such memory techniques are high, and to enable a computer to handle information from the outside more flexibly is considered an essential technique. To achieve such techniques, a storage circuit needs to have a function of measuring a degree of similarity between stored data and input data. In an approximate-search-circuit, a memory matrix of a conventional storage circuit is caused to function as a data conversion circuit for calculating the inner-product distance between stored data and input data, by inputting the input data to the memory matrix in the form of a time series of pulse-signals, and the location of stored data with the highest inner-product is output from a circuit that calculates the inner-product in real time.

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

Abstract: A semiconductor storage device of an embodiment includes: a plurality of columnar bodies that penetrate a predetermined film; and a beam that reaches a predetermined depth of the predetermined film shallower than depths of the plurality of columnar bodies and couples the plurality of columnar bodies together with a width smaller than widths of the plurality of columnar bodies.

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

Abstract: A memory device and an operating method for computing-in-memory (CIM) are provided. The memory device for CIM comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit. Each of the memory banks comprises a first memory array, a first latch circuit, a second latch circuit and a local MAC circuit. The first latch circuit latches a first data from the first memory array in a first read cycle. The second latch circuit latches a second data from the first memory array in a second read cycle. The local MAC circuit performs a first stage CIM operation on a first latched data latched in the first latch circuit and the second latched data latched in the second latch circuit to provide a first stage CIM result. The global MAC circuit performs a second stage CIM operation on a plurality of first stage CIM results from the memory banks.

Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer. A plurality of convolution engines each perform a convolution operation by applying a filter to a data window. Each of the plurality of convolution engines includes multiplication logic that combines a weight of a filter with a respective data value of a data window; control logic that receives configuration information identifying a set of filters for operation on a set of data windows at the plurality of convolution engines; determines a sequence of convolution operations for evaluation at the multiplication logic; requests weights and data values for at least partially applying a filter to a data window; and causes the multiplication logic to combine the weights with their respective data values. Accumulation logic accumulates the results of a plurality of combinations performed by the multiplication logic to form an output for a convolution operation of the determined sequence.

Abstract: A computer implemented method of storing and retrieving feature map data of a neural network the method comprising receiving a first portion of feature map data from local storage, selecting a first set of subportions of the first portion of feature map data, compressing the subportions to produce a first plurality of sections of compressed feature map data and instructing the storage of the sections into external storage. The method also comprises receiving a second plurality of sections of compressed feature map data from the external storage, decompressing the sections to produce a second set of subportions of the second portion of feature map data and storing the second portion of feature map data in local storage. The first and second sets of subportions each correspond to a predetermined format of subdivision and the method comprises selecting the predetermined format of subdivision from a plurality of predetermined formats of subdivision.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

Abstract: A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.

Abstract: Numerous embodiments are disclosed for programmable output blocks for use with a VMM array within an artificial neural network. In one embodiment, the gain of an output block can be configured by a configuration signal. In another embodiment, the resolution of an ADC in the output block can be configured by a configuration signal.

Abstract: A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

Abstract: Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.