Abstract: Devices are disclosed. A device may include an interface region including two or more input circuits operably coupled to the number of input signals, wherein one of the two or more input circuits for each input signal is adjacent at least two other input circuits coupled to different input. Associated systems are also disclosed.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.

Abstract: A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.

Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.

Abstract: A memory system includes a memory device including a plurality of blocks, a buffer storing degradation information regarding at least one of the plurality of blocks, and a memory controller configured to determine a degradation level of the block corresponding to the read request based on the degradation information, in response to a read request from a host, infer a read level corresponding to the read request based on the degradation level, and read data from the memory device based on the read level.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: An optical device for a quantum random number generator comprising: a source of phase randomised pulses of light, the source of phase randomised pulses of light further comprising a plurality of gain-switched lasers, each gain-switched laser having an output, and each gain-switched laser being configured to emit a stream of pulses such that the phase of each pulse in the stream of pulses is randomised, and an optical pulse combiner, the optical pulse combiner being configured to receive streams of pulses from the output of each gain-switched laser, combine the streams of pulses with one another into a combined stream of pulses and direct the combined stream of pulses into at least one output of the optical pulse combiner, the at least one output of the optical pulse combiner being the output of the source of phase randomised pulses of light; wherein the source of phase randomised pulses of light is configured such that the streams of pulses of light emitted by the plurality of gain-switched lasers are tem

Abstract: Systems and methods relate to arranging atoms into 1D and/or 2D arrays; exciting the atoms into Rydberg states and evolving the array of atoms, for example, using laser manipulation techniques and high-fidelity laser systems described herein; and observing the resulting final state. In addition, refinements can be made, such as providing high fidelity and coherent control of the assembled array of atoms. Exemplary problems can be solved using the systems and methods for arrangement and control of atoms.

Abstract: The disclosure describes various aspects of optical control of atomic quantum bits (qubits) for phase control operations. More specifically, the disclosure describes methods for coherently controlling quantum phases on atomic qubits mediated by optical control fields, applying to quantum logic gates, and generalized interactions between qubits. Various attributes and settings of optical/qubit interactions (e.g., atomic energy structure, laser beam geometry, polarization, spectrum, phase, background magnetic field) are identified for imprinting and storing phase in qubits. The disclosure further describes how these control attributes are best matched in order to control and stabilize qubit interactions and allow extended phase-stable quantum gate sequences.

Abstract: Embodiments of the present invention provides a system and method of learning and classifying features to identify objects in images using a temporally coded deep spiking neural network, a classifying method by using a reconfigurable spiking neural network device or software comprising configuration logic, a plurality of reconfigurable spiking neurons and a second plurality of synapses. The spiking neural network device or software further comprises a plurality of user-selectable convolution and pooling engines. Each fully connected and convolution engine is capable of learning features, thus producing a plurality of feature map layers corresponding to a plurality of regions respectively, each of the convolution engines being used for obtaining a response of a neuron in the corresponding region.

Abstract: Systems, apparatuses and methods include technology that identifies whether a product of first and second digital numbers is associated with a positive value or a negative value. During a first clock phase, the technology sets a first reference voltage to have a first value or a second value based on whether the product is associated with the positive value or the negative value. During the first clock phase, the technology controls switches to supply the first reference voltage to first plates of capacitors. Each of the capacitors includes a respective first plate of the first plates and a second plate. Further, during the first clock phase, the technology controls the switches based on the first digital number to electrically connect at least one of the second plates to the first reference voltage and electrically connect at least one of the second plates to a second reference voltage.

Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: A storage device may include: a memory device including a temperature sensor; and a memory controller for acquiring, from the memory device, temperature information sensed by the temperature sensor for a temperature management period, performing a performance limiting operation of limiting the performance of the memory device according to the temperature information, calculating the temperature management period by using the temperature information, and updating the temperature management period by using history information on a performance history of the performance limiting operation.

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.

Abstract: A system for operating a floating-to-fixed arithmetic framework includes a floating-to-fix arithmetic framework on an arithmetic operating hardware such as a central processing unit (CPU) for computing a floating pre-trained convolution neural network (CNN) model to a dynamic fixed-point CNN model. The dynamic fixed-point CNN model is capable of implementing a high performance convolution neural network (CNN) on a resource limited embedded system such as mobile phone or video cameras.

Abstract: An example method of implementing a quantized neural network (QNN) for a programmable device includes: identifying multiply-accumulate operations of neurons in the QNN; converting the multiply-accumulate operations to memory lookup operations; and implementing the memory lookup operations using a pre-compute circuit for the programmable device, the pre-compute circuit storing a pre-computed output of a neuron in the QNN for each of the memory lookup operations.

Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

Abstract: A memory array includes a plurality of column segments, each column segment including a plurality of columns of memory cells, a plurality of sense amplifiers selectively coupled to each column of the plurality of columns of a corresponding column segment, pluralities of first and second reference cells, and a reference current circuit. The reference current circuit generates a reference current based on a first current generated by a first reference cell programmed to a low logical value and a second current generated by a second reference cell programmed to a high logical value. Each sense amplifier generates a mirror current based on the reference current, and a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment.