Abstract: A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double suffering techniques allows use of a single, common shift clock instead of a series of staggered strobes a required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. "check" or parity date) "on the fly" during a write operation to a RAID array.

Abstract: A comparator circuit for differential output signals which is not affected by a common mode noise on the differential signals. The comparator circuit is advantageously used for testing differential output signals from a device under test (DUT). The comparator circuit includes an offset circuit for receiving differential signals from the DUT and generating a pair of balanced output signals which is provided with a predetermined offset voltage therebetween, and a comparator for receiving the pair of output signals from the offset circuit and comparing voltages between the output signals.

Abstract: In an (de)-interleaver (201) for J long subsequences (640-646) of data units (612), FIFOs are mapped into a memory (245) in such a way that locations (240) needed for one FIFO are moving through the memory (245). A generator (208) modulo increments only a single pointer (p, 230) which activates memory locations (240-p). Thereby, increments .DELTA.j correspond to FIFO sizes. For some p, (de)-interleaver (201) reads (25) a data unit (612) from a location (240) and than writes a new data unit (612) into that location (240), thus saving set-up times to establish a pointer. Also, the (de)-interleaver (201) needs only a number of memory locations K=(D-1 ) corresponding to a (D-1) interleaving depth. The (de)-interleaver (201) as part of a system (200) is fully programmable and can transfer data in two directions. Also, (de-) interleaving parameters (D-1) and J can be reconfigured during data transmission.

Abstract: An electronic device operates with an external accessory by initiating a serial data communication over an accessory control bus. If data communication is established with the external accessory, the electronic device operates in a first interface mode, when one or more operating parameters are transferred over the bus. If data communication is not established, the electronic device operates in a second interface mode, when no operating parameters are transferred over the bus.

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found.

Abstract: A method and apparatus for testing a RAM BIST controller by initializing a RAM behavior model with known fault data, running a RAM BIST controller model along with the RAM behavior model, and then comparing the output of the RAM BIST controller model with the known fault data to determine if there are any differences. A difference will indicate a fault in the RAM behavior model. The accuracy of the RAM BIST controller can then be used to compare the design of the RAM BIST controller with designs for other RAM BIST controllers in order to find the ideal RAM BIST controller for the intended purposes.

Abstract: A general purpose control system for use in the oilfield pressure pumping service industry. The system is comprised of a dedicated control computer mounted on the apparatus to be controlled and one or more remote operator units. The dedicated control computer interfaces with all the sensors and control elements of the apparatus. The control computer performs all the calculations necessary to control the apparatus. The dedicated control computer communicates with other computerized equipment on the apparatus such as engines, pressure sensors, speed sensors and flowmeters to extract data and perform control functions. The dedicated control computer has no operator controls. The dedicated control computer communicates via a single electrical cable to the operator control pendants. The control pendant is a small portable unit that provides the complete operator interface.

Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of foreign material, a defect or the like at the surface of a semiconductor wafer by a defect inspecting apparatus is stored. Also stored is data of physical coordinates obtained based on fail bit data from a tester. Data indicating an additional failure region is produced by an additional failure region estimating apparatus based on the fail bit data, and is stored. Collation produces data of corrected physical position coordinates by adding the stored data of limitation by failure mode to the stored data of physical position coordinates, and collates the data of corrected physical position coordinates with stored data of defect position coordinates. Accordingly, accuracy in collation is improved, and failure can be analyzed even if caused not by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure.

Abstract: A microprocessor (10) and system (2) are disclosed, in which capability for the detection and handling of modifications of instructions potentially in the pipeline is implemented. The microprocessor (10) includes a self-modifying code (SMC) unit (50) that includes a fetch address window maintenance unit (52), a write comparator (54) associated with each load/store unit (40) in the microprocessor (10) that performs writebacks to memory (16, 11, 5), and a shared write comparator (55). The fetch address window maintenance unit (52) includes a minimum latch (60) that stores the lowest fetch address since a pipeline flush or machine reset, and a maximum latch (62) that stores the highest fetch address since flush or reset, and updates the minimum and maximum latches (60, 62) upon detecting that the current fetch address (LASTFA) falls outside of the current window.

Abstract: A decoding apparatus and a decoding method are capable of minimizing degradation of the quality of images and sounds when a synchronous signal error occurs. The decoding apparatus includes a frame counter for receiving a bit stream, a synchronous pattern detector, a data error check unit, a synchronous detector, and a frame error determination unit. A synchronous detection error occurrence signal produced by the synchronous detector is not output to an external error processing circuit but is directly transmitted to the frame error determination unit. Even when the timing of an output synchronous pattern detection signal from the synchronous pattern detector and the timing of an output frame position signal from the frame counter do not match each other and a frame synchronous abnormality occurs, if the data itself is normal then decoding processing is executed without performing any error correction processing.

Abstract: A method of recovering a lost or corrupted data packet of a plurality of data packets transmitted by a transmitting computer system to a target computer system over an unreliable computer network. In one embodiment, the transmitting computer system generates parity information by padding the plurality of data packets to the length of the longest data packet with a suitable bit pattern. The parity information is then generated using a suitable algorithm, such as an exclusive OR (XOR) operation. The parity information and the packet lengths of the data packets are used to form the parity packet. The transmitting computer system then sends both the data packets and the parity packet to the target computer. If the target computer system detects a lost or corrupted data packet, the target computer attempts to reconstruct the lost or corrupted data packet. The received uncorrupted data packets are padded with the suitable bit pattern described above.

Abstract: An error correction decoder for correcting errors in digital data includes an address generation circuit capable of generating addresses for accessing a first buffer memory and a second buffer memory. The first buffer memory preferably stores user data, and the second buffer memory stores parity code data associated with the user data. An input controller receives input data and stores the input data in the first and second buffer memories in accordance with the addresses generated by the address generation circuit. An error correction circuit receives user data and associated parity code data, performs error correction, and rewrites the corrected data and parity code data back to the respective memory areas. An output controller then read the error-corrected user data from the first buffer memory.

Abstract: A bidirectional FILO capable of continuously performing the function of the FILO for different groups of codes is used to reduce a circuit scale of a Reed-Solomon error correcting device. Coefficients of an error-locator polynomial .delta.(x) and an error-evaluator polynomial .omega.(x) obtained by using a Euclid method are obtained in order from a final digit of a code to a first digit thereof. Correspondingly, a corrector starts a Chien search in order from a final byte of the code to a first byte thereof. In response to the order of the search, each group of data RSIN (Reed-Solomon Input) having digit order reversed in a bidirectional FILO are given to the corrector. The code corrected by the corrector also has digit order reversed. Therefore, the digit order is returned to original order in the bidirectional FILO for returning digit order to original order, so that a code RSOUT (Reed-Solomon Input) is output. The bidirectional FILOs can be implemented by operation of a shift register type, for example.

Abstract: A medical system e.g. for diagnosing and/or treating a patient has a system controller for controlling the system-specific components. The controller works together with an input device and is additionally assigned a data storage unit in which it is possible to store at least one operating menu. The operating menu can be called up by means of the input device and can be displayed on an indicating or display device. The operating menu includes a plurality of operating functions which can be selected, e.g., by means of a movable marker. When an operating function is selected its associated executable function is executed under control of the system controller. The system is further provided with the functionality of allowing a user to freely select specific operating functions from among the totality of operating functions assigned to the one or more operating menus and store the selected functions in the data storage device grouped as a separate, independent operating menu.

Abstract: The present invention relates to multiprocessors which has several microprocessors on a single chip. Efficiency is improved by stripping certain functions that are used less freely from the microprocessor and sharing these functions between several symmetric microprocessors. This method allows each CPU to occupy a smaller area while preserving complete symmetry of capability for software simplification. For example, the shared execution units can include the floating point unit and multimedia execution units.

Abstract: A window signal generating circuit generates a window 1 signal in synchronization with a reference counter and generates a window 2 signal by inverting the window 1 signal. If a detected synchronizing signal detected by a synchronizing signal detecting circuit is synchronized with a window 1 signal, a resynchronizing signal output circuit outputs a resynchronizing signal in synchronization with the window 1 signal. If a window 1 signal and a synchronizing signal are not synchronous, that is, if a window 2 signal is at a high level and a synchronizing signal is detected, another reference counter is synchronized with the synchronizing signal, and if a synchronous state continues by a predetermined frequency or more, the reference counter is synchronized with the timing of another reference counter. A synchronizing signal can be promptly fetched by the above processing.

Abstract: A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons.

Abstract: A Viterbi calculator performs additions in parallel with comparison to compute the result of a single Viterbi equation in a single clock cycle. Therefore, the results of a butterfly operation involving two Viterbi equations can be computed in a single clock cycle by use of two Viterbi calculators. Alternatively, the butterfly operation can be implemented by a single Viterbi calculator used in a pipelined manner, although the throughput is at the rate of every two clock cycles. When a single Viterbi calculator is used in the pipelined manner, two multiplexers are used to alternately swap the constant values being supplied to the Viterbi calculator. The pipelined use of a single Viterbi calculator requires less space on an integrated circuit die than the parallel use of two Viterbi calculators, and is useful in applications where the variable data is available every two clock cycles (e.g. due to latency in accessing memory).

Abstract: Methods and associated apparatus within a RAID subsystem having redundant controllers define a private LUN as a data storage area known and accessible to all controllers in the system and used by them for diagnostic purposes. The methods involve sending a diagnostic write command to a first controller with instructions for it to write test data to the private LUN. This first controller writes this test data to the private LUN. A second controller, in response to another diagnostic command, then reads this test data from the private LUN and compares it to expected values provided in the diagnostic command. Using the results, it can then be determined which controller, if any, failed. If the first controller fails, then the second controller takes over ownership of portions of the data storage area assigned to the first controller. The private LUN is preferably striped across all channels used by the controllers to communicate to commonly attached disk drives.

Abstract: This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC.sub.-- RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC.sub.-- RSs corresponding to one or more RSB elements into a matrix such that each SBRIC.sub.-- RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC.sub.-- RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC.sub.-- RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.