Abstract: A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.

Abstract: A broadcasting method encodes program material using convolutional codes having non-puncturable bits and puncturable bits and modulates orthogonal frequency division multiplexed carrier signals with the convolutional codes. The non-puncturable bits are carried by a first group of the carriers and the puncturable bits are carried by a second group of the carriers, where the first group of carrier signals is less susceptible to interference than the second group of carrier signals. The carrier signals are then broadcast to receivers which determine if the carriers in the second group have been corrupted and erase puncturable bits carried by any of the carriers which have been determined to be corrupted. This produces punctured codes which are subsequently decoded to recover the program material.

Abstract: A voltage regulator is disclosed which is coupled with a programmable trimming circuit by a trim test circuit. When disabled, the trim test circuit passes the logic states of the signals produced by the trimming circuit to the voltage regulator. When enabled, the trim test circuit applies signals to the voltage regulator which correspond with asserted logic states of signals producible by the trimming circuit. Thus, the effect of the trimming circuit on the voltage regulator is testable without actual programming of the trimming circuit.

Abstract: A variety of FIFOs, including single and dual port, RAM-type and/or having a ring-type addressing mechanism, are tested by causing the FIFOs to execute a test method comprised of a series of steps. Upon execution, the steps cause the FIFO to manifest a variety of faults. This test method manifests faults by monitoring the outcome of operations and the values of particular flags indicative of normal FIFO operation.

Abstract: A memory circuit, provided with address signal generating arrangement that includes first counter 72 for outputting first output data Q1 sequentially designating address signals for memory cells under test in a memory 10, a second counter 74 for outputting second output data Q2 used to designate address signals for each memory cell of the memory 10 for every cell under test, an output control circuit 76 for selectively outputting the second output data Q2 as third output data Q3 depending on a control signal INH, and a computing circuit 78 for carrying out computations based on the first output data Q1 and the third output data Q3, and generating address signals Q4. In this way, a memory receives address signals based on a test pattern, and a tester exclusively for memory tests is not required.

Abstract: A method for sending messages from a lower-level controller to a higher-level controller wherein a respectively different message is initially transmitted via a respective transmission path, a respective acknowledgment of the receipt of a respective message is returned along each respective transmission path, and a further message is then transmitted via the respective transmission path by which the respective acknowledgment was received.

Abstract: An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal.

Abstract: A method and apparatus in which on-chip functions are checked and any detected anomalies are located within a nested time interval. An on-chip function is tested by (1) applying a predetermined data pattern to the function, (2) computing a linear block error detection code residue from any output from the function being tested, and (3) comparing the residue to a error code residue (signature) derived from the output of a copy of the same function with the same data pattern. In one embodiment, the code signature has been previously derived from an error-free copy of the function. Where the signature is supplied contemporaneously by another copy of the same function also being tested, the function copy is not presumed error free. In both cases, any mismatch between the on-chip code residue and the signature indicates error, erasure, or fault. By either recursive reprocessing or shortening the intervals between comparisons, the mismatch can be located within a nested time or sequence interval.

Abstract: An LSI tester having a path analysis means for tracing a series of connections reversely along a designated signal flow path from one of flip-flops of DUT (device under test) at which flip-flop an inconsistency in pattern value has been detected as a consistency detection point by an output pattern comparator, based on circuit information in DUT, and for identifying firstly reachable flip-flops or external terminals from the inconsistency detection point as arrival points. And a sequence-pattern-inverting means sequentially inverts at least partly the values of successive test patterns one at a time with respect to each of the arrival points. The fault position in DUT is narrowed down from the arrival points simply in a shorter time.

Abstract: In an error correcting system, an error correcting unit stores a subframe data sequentially and circularly in first to third subframe memories. The subframe data is supplied continuously and is subjected to a first row direction error detecting and correcting process. The error correcting unit performs a column direction error detecting and correcting process to first and second subframe data and then performs a second row direction error detecting and correcting process to a part of the first subframe data, while the first row direction error detecting and correcting process is performed to a third subframe data to store in the third subframe memory. Also, the error correcting unit performs the second row direction error detecting and correcting process to a remaining part of the first subframe data and the second subframe data, while the first row direction error detecting and correcting process is performed to a fourth subframe data to store in the first subframe memory from a head location.

Abstract: An asynchronous integrated circuit (IC) tester includes a set of channels interconnected by a runtime bus. Each channel accesses a separate terminal of an IC device under test (DUT) for carrying out test activities during successive cycles of a test. During each cycle of a test, each channel may transmit a test signal to the DUT, sample a DUT output signal and store sample data representing the logic state of the DUT output signal, and/or compare previously stored sample data to expected patterns to determine if the DUT is operating correctly. Any channel may be programmed to place a MATCH code on the runtime bus when it recognizes, or fails to recognize, a particular logic pattern in the DUT output signal. Other channels may be programmed to pause their comparison activities until they receive the MATCH code over the runtime bus. Thus a DUT output signal event detected by any one channel triggers test activities by other channels.

Abstract: The purpose of the present invention is to provide a method for choosing the coding schemes, mappings, and puncturing rates for a modulation/demodulation system which would allow the system to compensate for certain transformations of the code in a post-Viterbi step as opposed to pre-Viterbi. This would allow for faster and simpler decoding of a code.

Abstract: A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM.

Abstract: In process controlling computers, such as switching exchanges, faults may prove to be very expensive. Particularly hard to solve are software defects. If problems occur, it is important that maintenance can be directed at the correct target as soon as possible. A threat is constituted by vandals and hackers. If the option for maintaining from elsewhere is incorporated in computers, the danger for misuse consequently increases. Prior art techniques for detecting memory problems do not necessarily reveal defects occurring at regular intervals caused by the method of calculation. Memory defects will occur at regular intervals e.g., if an address line of a memory circuit becomes faulty. A second drawback of the prior art is that the checksum has to be calculated anew if the contents of just one storage location change. The method of detecting memory problems according to the invention is "regularly irregular" so that it detects in a reliable manner an uncontrolled change in any storage area (MA).

Abstract: A data-reproducing device is provided that, even when pre-equalization characteristics are varied, conducts an equalization detection operation. The device comprises a subtraction absolute value circuit for calculating a subtraction absolute value, a comparison and selection circuit that outputs a selection signal to show which path is selected, a circuit that stores an estimate of the pre-equalized data, an address generating circuit that provides estimate data needed by the subtraction absolute value circuit as determined by the selection signal, a path memory circuit for storing the selection signal output and outputting the most probable data, and a correction control circuit for renewing the estimate data of the estimate data storing circuit.

Abstract: Disclosed is the selecting of permutations of a plurality of parameters, each parameter comprising a plurality of parameter values, for applying the selected permutations as a permutation sequence to a device under test DUT. At first, a cycle size representing the number of parameter values in a parameter cycle to be repeated successively in the permutation sequence is defined for each parameter. The following criteria have to be met: a) the cycle sizes have to be different for all parameter cycles, b) each cycle size has to be equal or greater than the number of different parameter values of the respective parameter, and c) two cycle sizes must not have one or more factors in common. Each parameter cycle is provided with parameter values from that parameter according to the defined cycle size, and the parameter cycles can be repeated concurrently, preferably until a given termination criterion is reached all possible permutations have been selected.

Abstract: According to the present invention, an LFSR (300) has a propagation path (30) of serially coupled stages (65) and gates (80-3, 80-4), a feedforward path (10) of gates (80-1) and a feedback path (20) of gates (80-2). Depending on control signals (P, B, M), the gates (80-1, 80-2, 80-3, 80-4) are either active gates and operate as xor-gates or passive gates and operate as transfer gates. Feedforward and feedback signals are derived from input and output signals and can be supplied to any stage (65), so that characteristic polynomials of the input-output function are variable. The LFSR can fully or partly operate as a TYPE 1 or TYPE 2 LFSR which enables the execution of different algorithms on one hardware base.

Abstract: A sufficient and necessary number of operation cycles for detecting faults, which have not been found by a function test, are accurately and rapidly selected by performing a logical simulation of an operation of an integrated circuit including m internal nets. A fault simulation is performed by using a predetermined test pattern so as to specify internal nets for which a fault is detected. Standby cycles are detected from among operation cycles in the logical simulation. .alpha. internal nets at which a fault is detected by the fault simulation from among the m internal nets to be subjected to the IDDQ test are excluded. The standby cycles are selected as the IDDQ test cycles based on the (m-.alpha.) internal nets.

Abstract: A Trellis decoder allows for real time decoding of high rate input data more than 10 MHz, with a compact layout and without the need to generate very high speed clocks, by use of a branch metric generator feeding multiple parallel Add/Compare/Select modules, which in turn feed a traceback processor using pre-traceback shift registers and traceback memory. The decoder performs n-state Trellis decoding in real time while simultaneously de-interleaving a multiplexed data stream. The architecture can be expanded to provide programmable length traceback in a fixed number of clock cycles. The invention performs de-interleaving in parallel with the Trellis decoding, and symbols coming out of the decoder need no further processing for de-interleaving. Moreover, the invention allows complete traceback in one symbol period at video rates without the need for very high speed clocks or multi-read port memories. Programmability allows for flexible tradeoff of output error rate and traceback memory space.

Abstract: In a communication network, a method for channel quality estimation, without the need for a reference (uncorrupted) signal, comprises the steps of: processing a received signal utilizing a non-redundant error correction scheme to observe at least one symbol; producing an error signal in response to the observation; and counting a quantity of the error signal during a predetermined time interval to provide a symbol error count. A device for channel quality estimation, without the need for a reference (uncorrupted) signal, is also described.