Abstract: A carrier recovery circuit is disclosed for use in the receiver of a digital transmission wherein channels of data are formed by demodulating incoming quadrature-related carriers using receiver-generated, quadrature-related carriers. Phase alignment of the receiver-generated carriers to the incoming carriers is provided by integrated data from a preselected channel when the channels of data correspond to preselected regions in the signal space diagram.

Abstract: An n-dimensional channel code is used in a data transmission system. The alphabet of codewords (data symbols) comprises a subset of points of a selected coset of a selected lattice. The alphabet includes at least one point of the coset whose norm (signal energy) is greater than at least one other point of the coset which is excluded from the alphabet.

Abstract: An improved digital demodulator and detector for phase-shift-keyed digital signals providing coherent detection with high sensitivity and stability on noisy channels. Digital sampling is used in conjunction with a digital phase locked loop system in which basic time increments are subtracted or added to an equilibrium timing loop to provide simultaneous carrier demodulation and bit recovery.

Abstract: A multipath interference reduction system for mobile subscriber access systems, each occupying one of a plurality of time slot channels. Interference caused by multipath returns is eliminated in the receiver portion of digital signal communications apparatus by a plurality of cascaded signal subtraction units wherein the detected signal is successively delayed by increasing multiples of the pulsewidth of the main lobe, varied in amplitude and subtracted from itself until all the multipath amplitudes of significance are subtracted out of the composite received signal.

Abstract: Expanded multiplexed noise codes formed from code mate pairs of equal code length and having autocorrelation functions which upon detection provides an impulse autocorrelation function are generated by delaying one of the code mate pairs (code b) by a time delay less than its code length and adding it to the other code mate pair (code a) to form a first expanded code mate (code A) while a second expanded code mate (code B) is generated by forming the complement of the delayed code b and adding it to code a. Such partial overlapping results in expanded codes which also compress to an impulse when detected with a matched filter. These expanded codes, moreover, are utilized in multiplexed noise code modulated communications systems.

Abstract: A synchronous circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect a sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signals and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit when noise is produced by the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter.

Abstract: This invention is a digital phase modulator for microwave transmitter systems. A digital signal is bandwidth limited at baseband, then is shaped to compensate for the nonlinear reflection coefficient versus bias voltage characteristics in a phase modulator. The shaped signal is applied to the phase modulator to modulate a carrier. The carrier signal is derived from a high power amplifier operating at its maximum power handling capability. Linear multiplication is then obtained, and use of linear intermediate frequency stages, up-converters as well as operation of the high powered amplifier at less than maximum power to obtain linear operation is thus avoided.

Abstract: A phase locked loop frequency synthesizer circuit for utilization in a broadband RF modem including a computer controlled transmit and receive function for use in the intertransmission of data on a local network comprising a plurality of the modems. According to the invention, a single phase locked loop frequency synthesizer circuit may be employed to establish both the transmit and receive frequencies, in addition to a method for the intertransmission of data between modems, in which data may be transmitted or received in a synchronous or asynchronous format on a local network.

Abstract: A noise reduction circuit comprising first and second variable frequency amplifiers (3, 4; 12, 13) for respectively amplifying first and second audio signals at variable gains in response to a control signal, a frequency splitter (23-26; 42-45) for splitting each output signal of the first and second variable gain amplifiers into high and low frequency components, an envelope detector (27-30; 46-49) for detecting the envelopes of the high and low frequency components of each audio signal and generating therefrom first and second high frequency component envelopes and first and second low frequency component envelopes, a combining circuit (31, 32; 50, 51) for combining the first and second high frequency component envelopes to generate a combined high frequency output and combining the first and second low frequency component envelopes to generate a combined low frequency output, and means (33-35; 52-54) for integrating the combined high frequency output with a smaller time constant and integrating the combine

Abstract: Undesired intentional interference, i.e. jamming signals in a multiple acsing mobile subscriber system employing a plurality of subscriber communication terminals, selectively transmitting and receiving desired signals from one another via a central node or repeater station, is achieved by intercepting relatively strong jamming signals, also directly received by the various subscriber communication terminals, and transmitting the jamming signals to the central node where they are then retransmitted or relayed to the subscriber terminals in a dedicated orthogonal multiplexed channel relative to respective signal channels carrying desired communications signals. Each terminal includes means for demultiplexing the orthogonal channel and the signal channel. The relayed jamming signals are adjusted in amplitude and time position so that they are equal to and coincident in time with the directly received jamming signals.

Abstract: Method and apparatus for generating a series of delta modulation data signals corresponding to a predetermined analog waveform wherein an error determination comparison is made on a sequentially generated series of potential delta modulation data signals to determine the optimum pattern of delta modulation bits. The method can be performed in iterative fashion for each delta modulation bit generated.

Abstract: A noise reducing apparatus comprises a first variable gain control circuit for giving a level compression characteristic to an input signal by a first composite control voltage, to produce an output signal to a transmission path, a first control voltage producing circuit for dividing an output signal of the first variable gain control circuit into a plurality of frequency bands, and producing a plurality of control voltages respectively given with mutually different integration time constants for each of the divided frequency bands, a first adding circuit for respectively additionally composing the plurality of control voltages obtained from the first control voltage producing circuit, to obtain the first composite control voltage, a second variable gain control circuit for giving a level expansion characteristic complementary to the level compression characteristic to a level compressed signal obtained through the transmission path by a second composite control voltage, to produce an output signal, a second

Abstract: To obtain a duo-binary FSK modulation, the modulating binary signal train has a three state partial response and is fed through a precoding, a transition-type coding, a simplified MSK modulation at the carrier frequency, a frequency division by two, and a multiplication by the same signal delayed by one binary element period. In order to obtain a "tamed FSK" modulation, the modulating binary signal train has a five state partial response and is fed through precoding, a transition-type coding, a simplified MSK modulation at the carrier frequency, a frequency division by two, a multiplication by the same signal delayed, for one part, by one binary element period and, for the other part, by two binary element periods. A TFM modulation is obtained by using the FSK duo-binary generating process, but a wave shaping filter is connected between the division by two circuit and the multiplication circuit.

Abstract: A timing signal is generated from a received pulse-amplitude-modulated (PAM) signal by generating a delayed difference signal, multiplying the delayed difference signal by .+-.1 in accordance with a decision signal, averaging the multiplication output to control a voltage-controlled oscillator, and using the oscillator output to clock a sampler/comparator which compares the input signal to a predetermined threshold at time instants determined by the VCO output to generate the decision signal.

Abstract: A portable frequency modulation transmitter (1) for voice or data is disclosed for operation at infrared frequencies. The transmitter comprises keyboard (200) or microphone (402) input capability and dual modes of use. In the data mode, carrier is generated when the keyboard is operated and is not generated when the keyboard is idle in order to conserve power. In the voice mode, either voice or data may be transmitted, data having priority over voice. A series connection of two variable modulus counters (302, 303) and other counters (304, 305, 306) provide a frequency shift keyed data signal, marker data signal, marker data frames between data frames, parity insertion and other features. In the event that the local battery power level falls below a particular level, a particular word is inserted in the applied binary data input.

Abstract: A Differential Phase Shift Keyed (DPSK) receiver is arranged to detect DPSK signals that contain the O.degree. vector as an information bearing signal in its constellation. The received signal is phase shifted by 90.degree.. A 45.degree. phase shifted signal is thereafter synthesized by additively combining the DPSK signal and the 90.degree. phase shifted signal. Using these signals, detection proceeds by means of correlation techniques. The polarities of the correlation products uniquely determine the phase changes of the DPSK signal.

Abstract: Apparatus for extracting synchronizing information from an incoming serial-bit digital television signal formed of a sequence of data blocks, each block formed of N n-bit words and including within each block a predetermined serial group of m bits forming the synchronizing information, which identify each block of information and enable de-serialization of said signal. The apparatus comprises a first m-stage shift register through which the incoming digital signal is stepped at the bit rate of the incoming digital signal, and which supplies a pulse whenever it holds a predetermined serial group of m bits, a frequency divider to derive from the incoming digital signal a word rate clock pulse signal.

Abstract: A pulse regenerator is installed at a repeater having an equalizing amplifier for equalizing a ternary pulse sequence received from a transmission line. Responsive thereto, a first ternary pulse sequence is and with a phase that is the same as the phase of the equalized ternary pulse sequence. A second ternary pulse sequence has a phase which is the reverse of the phase of the equalized ternary pulse sequence. The pulse regenerator also receives a clock pulse sequence which is derived from the input ternary pulse sequence. A first timing signal having the same phase as the clock pulse sequence and a second timing signal having a phase which is the reverse of the phase of the clock pulse sequence is produced in response to the clock pulse sequence. The first and second ternary pulse sequences are compared with a predetermined value, in synchronism with the first timing signal, and the two comparison results are produced as an output.

Abstract: A data acquisition circuit is adapted to receive information data, a synchronization pulse and a clock pulse which is transmitted at twice as high as the transmission rate of the information data. The clock and synchronization pulses are processed into a conditioning pulse for a divide-by-two frequency divider so that it conditions the divider to respond to the clock pulse by generating a data acquisition pulse at a frequency corresponding to the transmission rate of the information data in a correct phase relationship therewith.

Abstract: In a reception system which includes a receiver having a plurality of inter-connected stages and a demodulator, and where there appears at an input of the receiver a desired signal which occupies substantially a predetermined bandwidth, and at least one undesired signal which occupies a bandwidth different from, though partially overlapping the predetermined bandwidth, the improvement includes a signal selector coupled to receiver terminals upstream of the receiver demodulator for normally continuously selecting one of the signals appearing across the receiver terminals, a gain-controlled feedback stage connected with one input thereof to an output of the signal selector for negatively feeding back to the receiver terminals one of the signals substantially 180.degree.