Abstract: Incoming data in binary form is retimed, and under control of a framing clock, a first counter clocks in four bits in the first stage of a preview store; and a second counter clocks in eight bits, four bits in each of the second and third stage of the preview store. The first bit in each instance is the framing bit for the next previous frame location and the second next previous frame location so long as an in-frame condition exists, and the frame control is in synchronism with the framing bits contained in the incoming data.The current data bit is compared with the bits appearing at the output of the first and second stages of the preview store to determine if the three bits comprise a valid framing sequence for a non-winking framing sequence in which any combination of the following frame bit indications may occur-F1 F0 F0 F1-where the number following the F indicates the state of the framing bit.

Abstract: A PCM signal interface apparatus comprises a buffer memory being capable of asynchronously writing and reading a PCM signal, means for inserting a frame marker to the PCM signal upon writing the PCM signal into the buffer memory, means for judging whether or not the frame marker is contained in an output signal read out of the buffer memory at a time that is designated by an external read frame position designating pulse, means for resetting all the contents in the buffer memory and temporarily stopping the supply of a writing clock and a reading clock to the buffer memory when the frame marker is not delivered out at the predetermined time, means for resuming the supply of the writing clock to the buffer memory by receiving a write frame position designating pulse, and means for resuming the supply of the reading clock to the buffer memory by receiving the frame position designating pulse at a predetermined time lapse after the resumption of the writing clock supply.

Abstract: A tester for the collision detector of a transceiver for a multiple access data communications network using carrier-sense collision detection for controlling access to the network. A squelch circuit is employed in the transceiver's transmitter for enabling and disabling the transmitter output. An end-of-transmission detector monitors the squelch circuit to detect the termination of a transmission. Upon termination of a transmission, a collision simulator circuit supplies to the transceiver's receiver a signal of predetermined amplitude and duration, to simulate the input the receiver gets when a collision actually occurs. If the receiver is working properly, it signals a collision to the host (i.e., computer, terminal, etc). If it does not receive the collision signal at the appointed time, the host knows that either the transceiver's collision detection circuit or the tester is not working.