Abstract: A method for data processing is disclosed. A blank state is determined for several data bits based on a majority decision. Each data bit is represented by a group of at least two memory cells. The at least two memory cells of this group are complementary cells of a differential read memory.

Abstract: A computer system generates snapshot backups of a virtual machine by creating a metadata snapshot and a backup snapshot. The computer system identifies a backup request for a virtual machine operating on a host computing system, initiates a backup snapshot of storage devices in use by the virtual machine, generates a metadata snapshot of a configuration of the virtual machine, and maintains the metadata snapshot in a data store.

Abstract: Provided are a computer program product, system, and method for using geographical location information to provision multiple target storages for a source device. A determination is made of a geographical location of the source device and a distance between the source device and each of the target storages and between each pair of target storages. A determination is further made of qualifying k-tuples of the target storages, wherein each k-tuple comprises a group of k target storages to which the source data is to be backed-up. A qualifying k-tuple has one target storage that satisfies a distance requirement with respect to the source device and a distance between any two target storages in the k-tuple satisfies the distance requirement. A selected qualifying k-tuple is indicated to use to backup the source data at the k target storages in the qualifying k-tuple.

Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Abstract: A storage tier manager creates different versions of a dataset backup for different retention periods. Each of the versions is distinctly identifiable despite initially representing a same dataset backup. One version can be referred to as a cached version of the dataset backup and another version can be referred to as a cloud version of the dataset backup. When the retention period expires for the cached version of the dataset backup, the storage tier manager migrates the cloud version of the dataset backup from the caching storage tier to the cloud storage tier. The storage tier manager can then recover storage space occupied by data that has been migrated, as long as that data is not shared with other cached versions of other dataset backups due to deduplication.

Abstract: Embodiments include methods, systems and computer readable media configured to execute a first kernel (e.g. compute or graphics kernel) with reduced intermediate state storage resource requirements. These include executing a first and second (e.g. prefetch) kernel on a data-parallel processor, such that the second kernel begins executing before the first kernel. The second kernel performs memory operations that are based upon at least a subset of memory operations in the first kernel.

Abstract: An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.

Abstract: One or more techniques and/or systems are provided for implementing storage level access control for data grouping structures. For example, a storage level access guard may be defined for a data grouping structure (e.g., a Qtree, a portion of a volume, etc.) of a storage device. The storage level access guard may be defined at a storage level of the storage device such that clients and/or certain administrators such as domain administrators may be restricted from accessing and/or changing the storage level access guard, which may increase data security. A hidden and unmodifiable property may be applied to the storage level access guard, which may be stored in a directory associated with the data grouping structure so that a logical replication of the data grouping structure may also replicate the storage level access guard.

Abstract: According to one embodiment, a memory system comprises a non-volatile semiconductor memory, a memory and a controller. The memory stores a management table including a plurality of parameters for managing the non-volatile semiconductor memory. The controller is configured to control the operation of the non-volatile semiconductor memory based on a first value of the parameters contained in the management table. The controller obtains a second value corresponding to the parameters from an operation log of the non-volatile semiconductor memory, compares the second value of the parameters with the first value, calculates the difference between the second value of the parameters and the first value when they are different from each other, calculates a correction value for correcting the first value when the difference is greater than a third value, and updates the first value of the management table based on the correction value.

Abstract: An arithmetic processing device includes clusters, each including cores and a last level cache shared by the cores; a home agent connected to the last level caches; and a memory controller connected to the home agent to control accesses to a memory. In response to a memory request from a first last level cache in a first cluster, the home agent issues a first replace request to the first last level cache to evict a first victim line in the first last level cache, the home agent issues a second replace request to a second last level cache in a second cluster in an idle state other than the first cluster to evict a second victim line in the second last level cache, and the second last level cache fills data of the first victim line to the second victim line.

Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.

Abstract: Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.

Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

Abstract: A system for improving utilization of a nonvolatile flash memory device which has pages whose guaranteed per-cycle erase time and guaranteed number of cycles are known, the system comprising erase time determination functionality for individual pages; de-facto total erase-time accumulation functionality incrementing, for each erase cycle to which an individual page is subjected, by the individual page's de facto erase time per cycle as provided by the erase time measurement functionality; and flash memory page usage monitoring functionality operative to control usage of pages in flash memory including selecting at least one individual flash memory page depending on a comparison between the individual flash memory page's de facto total erase time and a guaranteed erase time computed as a product of the guaranteed per-cycle erase time and of the guaranteed number of cycles.

Abstract: A method for use in a distributed storage network (DSN) includes receiving, by a performance unit, access requests from a distributed storage (DS) processing unit. The access requests identify one or more storage units to which access is requested. The performance unit determines that at least a first storage unit is associated with a status level that fails to satisfy a threshold value associated with the access requests, and that at least a second storage unit is associated with a status level that does satisfy the threshold value. For the at least a first storage unit, the performance unit facilitates execution of an alternative approach to processing an access request corresponding to the first storage unit, and for the at least a second storage unit facilitates execution of a standard approach to processing an access request corresponding to the second storage unit.

Abstract: The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

Abstract: A system and method for providing mutual exclusivity to an operation is presented. A memory location is checked to determine if the memory location is subject to an exclusive lock. If so, the age of the exclusive lock is determined. If the age of the exclusive lock is greater than a certain length of time, the exclusive lock on the memory location is released such that operations can be performed on the memory location. When a memory lock is created, a length of time can be associated with the memory location. The length of time can be a default length of time. The length of time can be a custom length that is stored in a database. Other embodiments also are disclosed.

Abstract: System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA controllers, a dual-port PCIE interconnection to two host processors of gateway clusters, and four switch fabric ports for interconnections with peer controllers (e.g., AFA blades and/or chassis) in the distributed flash storage network. The AFA storage blade includes dynamic random-access memory (DRAM) and magnetoresistive random-access memory (MRAM) configured as data read/write cache buffers, and flash memory DIMM devices as primary storage. Remote data memory access (RDMA) for clients via the data caching buffers is enabled and controlled by the host processor interconnection(s), the switch fabric ports, and a unified memory bus from the unified controller to the data buffer and the flash SSDs.

Abstract: An operating system monitors a performance metric of a direct memory access (DMA) engine on an I/O adapter to update a translation table used during DMA operations. The translation table is used during a DMA operation to map a virtual address provided by the I/O adapter to a physical address of a data page in the memory modules. If the DMA engine is being underutilized, the operating system updates the translation table such that a virtual address maps to physical address corresponding to a memory location in a more energy efficient memory module. However, if the DMA engine is over-utilized, the operating system may update the translation table such that the data used in the DMA engine is stored in memory modules that provide quicker access times—e.g., the operating system may map virtual addresses to physical addresses in DRAM rather than phase change memory.