Patents Examined by Alex G Olson
  • Patent number: 10348675
    Abstract: Systems, apparatuses, methods, and computer-readable storage mediums for performing lease-based fencing using a time-limited lease window. During the time-limited lease window, writes to a shared storage medium are permitted, while writes are denied for expired leases. When a successful heartbeat is generated for a primary storage controller, the lease window is extended for the primary storage controller from the time of a previous heartbeat. Accordingly, a prolonged stall between successive heartbeats by the primary storage controller will result in the newly extended lease being expired at the time it is granted. This scheme prevents a split brain scenario from occurring when a secondary storage controller takes over as the new primary storage controller in response to detecting the stall.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 9, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Joern Engel, Alan Driscoll, Neil Vachharajani, Ronald S. Karr
  • Patent number: 10339048
    Abstract: An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman Pletka, Sasa Tomic
  • Patent number: 10303618
    Abstract: An operating system monitors a performance metric of a direct memory access (DMA) engine on an I/O adapter to update a translation table used during DMA operations. The translation table is used during a DMA operation to map a virtual address provided by the I/O adapter to a physical address of a data page in the memory modules. If the DMA engine is being underutilized, the operating system updates the translation table such that a virtual address maps to physical address corresponding to a memory location in a more energy efficient memory module. However, if the DMA engine is over-utilized, the operating system may update the translation table such that the data used in the DMA engine is stored in memory modules that provide quicker access times—e.g., the operating system may map virtual addresses to physical addresses in DRAM rather than phase change memory.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventor: Justin K. King
  • Patent number: 10296469
    Abstract: Systems, apparatuses, methods, and computer-readable storage mediums for performing lease-based fencing using a time-limited lease window. During the time-limited lease window, writes to a shared storage medium are permitted, while writes are denied for expired leases. When a successful heartbeat is generated for a primary storage controller, the lease window is extended for the primary storage controller from the time of a previous heartbeat. Accordingly, a prolonged stall between successive heartbeats by the primary storage controller will result in the newly extended lease being expired at the time it is granted. This scheme prevents a split brain scenario from occurring when a secondary storage controller takes over as the new primary storage controller in response to detecting the stall.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: May 21, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Joern Engel, Alan Driscoll, Neil Vachharajani, Ronald S. Karr
  • Patent number: 10289563
    Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap. The hot-add RAM is split into at least two continuous parts.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay H. Akirav, Oren Bar, Roman Barsky, Itay Maoz
  • Patent number: 10248362
    Abstract: Managing data stored in at least one Data Storage Device (DSD) includes generating a Linear Tape File System (LTFS) write or read command including an LTFS block address. The generated LTFS command is for writing or reading data in an LTFS data partition, writing or reading metadata in the LTFS data partition, or writing or reading metadata in an LTFS index partition. The LTFS block address is translated to a device address for the at least one DSD using state metadata representing a state of the LTFS data partition and/or a state of the LTFS index partition. The data or the metadata is written or read in the at least one DSD at the device address.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 2, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: James N. Malina, Albert H. Chen
  • Patent number: 10222989
    Abstract: Providing for a multi-bank memory with bank-specific status feedback is described herein. By way of example, the multi-bank memory can be configured to output an availability status, pass/fail status, error correction status, or the like, for subsets of multiple memory banks. In some embodiments, the non-volatile memory can provide global status information, representing a status of all banks commonly in conjunction with bank-specific status information. Further, the subject disclosure provides addressing techniques for identifying particular banks of memory, and obtaining status information for subsets of the memory banks, or performing memory operations on targeted subsets of the memory banks.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 5, 2019
    Assignee: CROSSBAR, INC.
    Inventor: Cliff Zitlaw
  • Patent number: 10198352
    Abstract: Techniques for efficiently swizzling pointers in persistent objects are provided. In one embodiment, a computer system can allocate slabs in a persistent heap, where the persistent heap resides on a byte-addressable persistent memory of the system, and where each slab is a continuous memory segment of the persistent heap that is configured to store instances of an object type used by an application. The system can further store associations between the slabs and their respective object types, and information indicating the locations of pointers in each object type. At the time of a system restart or crash recovery, the system can iterate through each slab and determine, based on the stored associations, the slab's object type. The system can then scan though the allocated objects in the slab and, if the system determines that the object includes any pointers based on the stored pointer location information, can swizzle each pointer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 5, 2019
    Assignee: VMWARE, INC.
    Inventors: Pratap Subrahmanyam, Zongwei Zhou, Rajesh Venkatasubramanian
  • Patent number: 10176047
    Abstract: Provided are a computer program product, system, and method for using geographical location information to provision multiple target storages for a source device. A determination is made of a geographical location of the source device and a distance between the source device and each of the target storages and between each pair of target storages. A determination is further made of qualifying k-tuples of the target storages, wherein each k-tuple comprises a group of k target storages to which the source data is to be backed-up. A qualifying k-tuple has one target storage that satisfies a distance requirement with respect to the source device and a distance between any two target storages in the k-tuple satisfies the distance requirement. A selected qualifying k-tuple is indicated to use to backup the source data at the k target storages in the qualifying k-tuple.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Anglin, David M. Cannon, Colin S. Dawson, Howard N. Martin
  • Patent number: 10169233
    Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
  • Patent number: 10169234
    Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
  • Patent number: 10042563
    Abstract: In an all-flash storage array, write requests can take about 9 to 10 times longer than a read request of the same size. There could be several problems when reading or writing from all-flash storage, such as a large write request slowing down small read requests, or other write requests. Also, a large read request may slow down smaller read requests by filling the incoming requests queue. In one implementation, a determination is made on what is the maximum size of a request to flash storage that improves the throughput of a flash chip (e.g., write requests beyond a certain size do not improve throughput). A chunklet is defined as a block of data having the calculated maximum size. As write requests come in, the write requests are broken into chunklets, and then the chunklets are queued for processing by the flash chip. One chunklet is processed at a time per write request.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 7, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Anil Kumar Nanduri, Murali Krishna Vishnumolakala
  • Patent number: 10007438
    Abstract: A computing device having interface, memory, and processing module, transmits write requests for a set of encoded data slices to storage units (SUs) of a dispersed storage network (DSN) based on a write request process and to receive proposal records for a subset of the set of encoded data slices from at least some of the SUs. The computing device interprets the proposal records to determine whether it or any another computing device has a threshold number of its respective write requests in a first priority position in the ordered list of pending write requests. When no computing device has the threshold number, the computing device determines whether any computing device can be blacklisted and/or eliminated and whether a winner of the ballot can be determined after such determination. When a winner is determined, the computing device transmits finalize commands to the storage units.
    Type: Grant
    Filed: June 25, 2016
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Ravi V. Khadiwala, Ethan S. Wozniak
  • Patent number: 9959936
    Abstract: The present disclosure describes apparatuses and techniques that enable temperature-based memory access. In some aspects, a request to access a memory device is received. In response to the request, respective temperatures are determined for multiple locations of the memory device. Based on these respective temperatures, a selection can be made of which of the multiple locations to access. Alternately or additionally, an order in which to access the multiple locations can be determined based on the respective temperatures. The location(s) of the memory device are then accessed based on the selection or the determined order effective to minimize an increase in the memory device's temperature.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 1, 2018
    Assignee: Marvell International Ltd.
    Inventor: Jong-uk Song