Abstract: Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application. Another aspect includes creating a page table entry corresponding to the memory page in the page table. Another aspect includes determining, by a data fetch width indicator determination logic, the data fetch width indicator for the memory page. Another aspect includes sending a notification of the data fetch width indicator from the data fetch width indicator determination logic to supervisory software. Another aspect includes setting the data fetch width indicator in the page table entry by the supervisory software based on the notification. Another aspect includes, based on a cache miss in the cache memory corresponding to an address that is located in the memory page, fetching an amount of data from the memory page based on the data fetch width indicator.

Abstract: A multi-core CPU system includes a shared L2 cache, an access control logic circuit, a plurality of cores, each core configured to access the shared L2 cache through the access control logic circuit, and a size adjusting circuit configured to adjust a size of the shared L2 cache in response to an indication signal that indicates a number of operation cores among the plurality of cores.

Abstract: A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.

Abstract: In an all-flash storage array, write requests can take about 9 to 10 times longer than a read request of the same size. There could be several problems when reading or writing from all-flash storage, such as a large write request slowing down small read requests, or other write requests. Also, a large read request may slow down smaller read requests by filling the incoming requests queue. In one implementation, a determination is made on what is the maximum size of a request to flash storage that improves the throughput of a flash chip (e.g., write requests beyond a certain size do not improve throughput). A chunklet is defined as a block of data having the calculated maximum size. As write requests come in, the write requests are broken into chunklets, and then the chunklets are queued for processing by the flash chip. One chunklet is processed at a time per write request.

Abstract: Managing data stored in at least one data storage device (DSD) of a computer system where the at least one DSD includes at least one disk for storing data. A Linear Tape File System (LTFS) write or read command is generated including an LTFS block address. The LTFS block address is translated to a device address for the at least one DSD and data on a disk of the at least one DSD is written or read at the device address.

Abstract: Provided are a computer program product, system, and method for using geographical location information to provision multiple target storages for a source device. A determination is made of a geographical location of the source device and a distance between the source device and each of the target storages and between each pair of target storages. A determination is further made of qualifying k-tuples of the target storages, wherein each k-tuple comprises a group of k target storages to which the source data is to be backed-up. A qualifying k-tuple has one target storage that satisfies a distance requirement with respect to the source device and a distance between any two target storages in the k-tuple satisfies the distance requirement. A selected qualifying k-tuple is indicated to use to backup the source data at the k target storages in the qualifying k-tuple.

Abstract: Provided are a computer program product, system, and method for using geographical location information to provision multiple target storages for a source device. A determination is made of a geographical location of the source device and a distance between the source device and each of the target storages and between each pair of target storages. A determination is further made of qualifying k-tuples of the target storages, wherein each k-tuple comprises a group of k target storages to which the source data is to be backed-up. A qualifying k-tuple has one target storage that satisfies a distance requirement with respect to the source device and a distance between any two target storages in the k-tuple satisfies the distance requirement. A selected qualifying k-tuple is indicated to use to backup the source data at the k target storages in the qualifying k-tuple.

Abstract: A second memory allocator receives a request to allocate memory from a second process of the second memory allocator executing on a computer, and determines that memory for allocation to the second process is not available from a memory hoard of the second memory allocator. The second memory allocator determines that memory for allocation to the second process is not available from an operating system of the computer, and transmits the request to release memory to a first memory allocator. The first memory allocator of a first process executing on the computer receives the request from the second memory allocator executing on the computer to release memory. Responsive to the request from the second memory allocator to release memory, the first memory allocator releases hoarded memory previously hoarded for allocation to the first process.

Abstract: A method of operation of a storage control system includes: partitioning memory channels with memory devices; selecting a super device with one of the memory devices from one of the memory channels; selecting a super block associated with the super device; and determining a location of a parity within the super block when the super block is formed.

Abstract: A command is received to copy a first extent in a source volume to a second extent in a target volume, wherein the source volume and the target volume are in a copy relationship. In response to determining that it takes longer to copy all changed data of the first extent to the second extent than to copy all of the changed data of the first extent to a third extent and to copy all other data from the second extent to the third extent, operations are performed to copy all of the changed data of from the first extent to the third extent and to copy all of the other data from the second extent to the third extent. Operations are also performed to assign the third extent to replace the second extent in the target volume.

Abstract: A method begins by a processing module determining to move a range of encoded data slices from a first storage unit to a second storage unit of a plurality of storage units, where data objects are dispersed storage error encoded to produce pluralities of sets of encoded data slices, and where the pluralities of sets of encoded data slices are stored in the plurality of storage units. The method continues with the processing module transferring the range of encoded data slices from the first storage unit to the second storage unit. In response to the transferring the range of encoded data slices from the first storage unit to the second storage unit, the method continues with the processing module transferring a corresponding range of second encoded data slices from a third storage unit to a fourth storage unit.

Abstract: A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower maximum count defined by a predetermined lower maximum count of Task Control Blocks (TCBs) of a rank for performing destage operations, and a higher maximum count of TCBs to be implemented for performing a storage operation, and performs the storage operation using up to the lower maximum count of TCBs, yet only allows those TCBs above the lower maximum count to be allocated for performing the storage operation satisfying at least one criterion.

Abstract: A computer-implemented method for managing memory operations includes reading a first memory page from a storage device responsive to a request for the first memory page. The first memory page is stored to a system memory. Based on a pre-established set of association rules, one or more associated memory pages are identified that are related to the first memory page. The associated memory pages are read from the storage device and compressed to generate corresponding compressed associated memory pages. The compressed associated memory pages are also stored to the system memory to enable memory access to the associated memory pages during processing of the first memory page. The compressed associated memory pages are individually decompressed in response to the particular page being required for use during processing.

Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time for responding to an emergency by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap.

Abstract: A data storage device includes multiple flash memory devices with each of the flash memory devices being arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to mark one or more of the pages of the flash memory devices as available for deletion and maintain the marked pages as available for being read until deleted during garbage collection.

Abstract: Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature.