Patents Examined by Alex Olson
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Patent number: 9244857Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit (which may include a programmable hash table) may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the results. Each hash value may be used to access a location in a lookup table in memory to obtain its contents (e.g., a key and associated data). The circuit may include a selection sub-circuit that selects the data of one of the identified locations as an output of the lookup circuit (e.g., one whose key matches the input key). The circuit may modify obtained data prior to its selection and may output a signal indicating the validity of input keys.Type: GrantFiled: October 31, 2013Date of Patent: January 26, 2016Assignee: Oracle International CorporationInventors: Guy L. Steele, Jr., David R. Chase, Nils Gura
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Patent number: 9230620Abstract: A memory interface for a plurality of DRAM devices comprising an input DRAM address matching module includes a local memory comprising a plurality of data entries, wherein the plurality of data entries comprising a plurality of DRAM addresses and a plurality of associated pointers, and wherein the plurality of associated pointers comprise output DRAM addresses, and a matching mechanism coupled to the local memory, wherein the matching mechanism is configured to receive the input DRAM address, wherein the matching mechanism is configured to determine whether the input DRAM address is specified in the plurality of data entries, and when the input DRAM address is specified in the plurality of data entries, the matching mechanism is configured to output an associated pointer associated with the input DRAM address.Type: GrantFiled: March 1, 2013Date of Patent: January 5, 2016Assignee: INPHI CORPORATIONInventor: Chien-Hsin Lee
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Patent number: 9218277Abstract: A method for operating a computer memory. The memory is organized to store data in units of such memory. For each unit of a set of units a wear level of the unit is determined. A maximum wear level among the wear levels is determined. A suggestion of a subset of one or more units for being selected for data erasure is received and at least one unit in the subset is identified for subsequent data erasure, a wear level (c(i)) of which units (i) is less than the maximum wear level (c_max).Type: GrantFiled: May 11, 2012Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Giovanni Cherubini, Ilias Iliadis
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Patent number: 9195619Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The controller controls the memory, communicates with a host device via a first signal line and a second signal line, and receives data items to be written in the memory from the host device on the first and second signal lines in a first period. The same group number is assigned to two data items which flow in parallel on the first and second signal lines. The controller transmits to the host device a response packet including an indication of a group number assigned to an unsuccessfully received one of the data items.Type: GrantFiled: August 20, 2012Date of Patent: November 24, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Masahiro Sekiya
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Patent number: 9183147Abstract: A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.Type: GrantFiled: August 20, 2012Date of Patent: November 10, 2015Assignee: Apple Inc.Inventors: Manu Gulati, James D. Ramsay, Kevin R. Walker
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Patent number: 9183041Abstract: According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition.Type: GrantFiled: September 21, 2012Date of Patent: November 10, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Matthias Klein
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Patent number: 9183042Abstract: According to one aspect of the present disclosure, a method and technique for input/output traffic backpressure prediction is disclosed. The method includes: performing a plurality of memory transactions; determining, for each memory transaction, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determining a median value based on the determined traffic values; determining whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicating a prediction of a backpressure condition.Type: GrantFiled: November 11, 2013Date of Patent: November 10, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Matthias Klein
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Patent number: 9146857Abstract: A method for mapping management is disclosed. The steps of the method comprises sending data from a host; programming a host data a non-volatile storage device; updating a mapping address to a Physical Entry to Logical (PE2L) mapping table stored in a SRAM; updating a Physical Entry (PE) status table; checking if the PE2L mapping table is full; if no, loop to the step of programming a non-violate storage device; if yes, remove invalid entries in the PE2L mapping table and update the PE status table, and then run next step; transferring part of the PE2L mapping table to a Logical to Physical (L2P) mapping table stored in the non-volatile storage device; and programming the L2P mapping table to the non-volatile storage device and looping to the step of removing invalid entries in the PE2L mapping table and updating the PE status table.Type: GrantFiled: August 18, 2012Date of Patent: September 29, 2015Assignee: Storart Technology Co. Ltd.Inventor: Yen Chih Nan
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Patent number: 9146872Abstract: In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from AP.Type: GrantFiled: February 26, 2013Date of Patent: September 29, 2015Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, David W. Cummings, Michael S. Siegel, Jeff A. Stuecheli
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Patent number: 9141539Abstract: A system and method for object deletion in persistent memory using bitmap windows representing memory chunks. In accordance with an embodiment, the system can generally be used with computing environments that use persistent memory, such as smart cards, Java Cards, and other resource-constrained environments. In accordance with an embodiment, the system comprises a processor or computational engine and a persistent memory for storage of software objects; and a data structure which can include one or more memory bitmap windows, each of which represents a chunk of addressable space in the persistent memory; wherein the system uses the one or more memory bitmap windows in deleting non-reachable objects from the persistent memory.Type: GrantFiled: March 1, 2013Date of Patent: September 22, 2015Assignee: ORACLE INTERNATIONAL CORPORATIONInventor: Saqib Ahmad
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Patent number: 9135174Abstract: In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP.Type: GrantFiled: November 27, 2012Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, David W. Cummings, Michael S. Siegel, Jeff A. Stuecheli
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Patent number: 9047200Abstract: A method for managing redundancy of data in a solid-state cache system including at least three solid-state storage modules. The method may include designating one or more extents of each dirty mirror pair to be of a particular priority order of at least two priority orders. The at least two priority orders can include at least a highest priority order. The highest priority order can have a higher relative priority than the other priority orders. The method may also include performing at least one redundancy conversion iteration. Each redundancy conversion iteration includes converting extents of at least two dirty mirror pairs into at least one RAID 5 group and at least one unconverted extent. The extents of the at least two dirty mirror pairs can include extents designated to be of a highest remaining priority order. Each redundancy conversion iteration can also include deallocating the at least one unconverted extent.Type: GrantFiled: September 21, 2012Date of Patent: June 2, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Anant Baderdinni
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Patent number: 8990509Abstract: Embodiments herein relate to selecting an accelerated path based on a number of write requests and a sequential trend. One of an accelerated path and a cache path is selected between a host and a storage device based on at least one of a number of write requests and a sequential trend. The cache path connects the host to the storage device via a cache. The number of write requests is based on a total number of random and sequential write requests from a set of outstanding requests from the host to the storage device. The sequential trend is based on a percentage of sequential read and sequential write requests from the set of outstanding requests.Type: GrantFiled: September 24, 2012Date of Patent: March 24, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventor: Weimin Pan
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Patent number: 8930631Abstract: A system and a computer program product manages memory operations in a data processing system. The system includes a processor executing instructions that causes the processor to read a first memory page from a storage device responsive to a request for the first memory page. The first memory page is stored to a system memory. One or more associated memory pages are identified that are related to the first memory page by the set of association rules. The associated memory pages are read from the storage device and compressed to generate a corresponding compressed associated memory page. The compressed associated memory pages are stored to the system memory to enable memory access to the associated memory pages during processing involving the first memory page. The compressed associated memory pages are individually decompressed in response to the particular page being required for use during processing.Type: GrantFiled: August 20, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Saravanan Devendran, Kiran Grover