Patents Examined by Alexander Ghyka
  • Patent number: 10436742
    Abstract: In one implementation, a method for manufacturing a chemical detection device is described. The method includes forming a chemical sensor having a sensing surface. A dielectric material is deposited on the sensing surface. A first etch process is performed to partially etch the dielectric material to define an opening over the sensing surface and leave remaining dielectric material on the sensing surface. An etch protect material is formed on a sidewall of the opening. A second etch process is then performed to selectively etch the remaining dielectric material using the etch protect material as an etch mask, thereby exposing the sensing surface.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 8, 2019
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Shifeng Li, James Bustillo
  • Patent number: 10229987
    Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 12, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Kangguo Cheng, Zuoguang Liu, Ruilong Xie, Tenko Yamashita
  • Patent number: 10211291
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Patent number: 10205022
    Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 10204835
    Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10204790
    Abstract: In accordance with some embodiments herein, methods for deposition of thin films are provided. In some embodiments, thin film deposition is performed in a plurality of stations, in which each station provides a different reactant or combination of reactants. The stations can be in gas isolation from each other so as to minimize or prevent undesired chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) reactions between the different reactants or combinations of reactants.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: February 12, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Jun Kawahara, Suvi Haukka, Antti Niskanen, Eva Tois, Raija Matero, Hidemi Suemori, Jaako Anttila, Yukihiro Mori
  • Patent number: 10199537
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199535
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10186636
    Abstract: Device successively including a substrate including a metal layer capable of reflecting a radiation; a first layer of a III/N type alloy, p-type doped, and including a first surface, opposite the metal layer, the first surface being provided with cavities; a light-emitting layer made of a III/N-type alloy, capable of generating the radiation; a second layer of a III/N-type alloy, n-type doped, having the radiation coming out therethrough; wherein a non-metallic filling material transparent in the spectral range is arranged within the cavities.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 22, 2019
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Yohan Desieres
  • Patent number: 10177271
    Abstract: This disclosure provides systems, methods, and apparatus related to photodetectors. In one aspect, a photodetector device comprises a substrate, a polycrystalline layer disposed on the substrate, and a first electrode and a second electrode disposed on the polycrystalline layer. The polycrystalline layer comprises nanograins with grain boundaries between the nanograins. The nanograins comprise a semiconductor material. A doping element comprising a halogen is segregated at the grain boundaries. A length of the polycrystalline layer is between and separating the first electrode and the second electrode.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: January 8, 2019
    Assignee: the Regents of the University of California
    Inventors: A. Paul Alivisatos, Miquel Salmeron, Yingjie Zhang, Daniel J. Hellebusch
  • Patent number: 10170361
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert L Bruce, Cyril Cabral, Jr., Gregory M Fritz, Eric A Joseph, Michael F Lofaro, Hiroyuki Miyazoe, Kenneth P Rodbell, Ghavam G Shahidi
  • Patent number: 10170371
    Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 10170319
    Abstract: A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: January 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita
  • Patent number: 10161660
    Abstract: The device provides the possibility of feeding test signals to a thermoelectric module by virtue of the use of controllable switches and also makes it possible to increase test criteria and to detect faults and the causes of said faults at early stages outside of the use process of the thermoelectric module (TEM), as well as in periods between use. This technical result is achieved in that the device comprises a DC source, a measurement circuit, a first, a second, a third and a fourth controllable switch, which are used for feeding test signals and are switched on and off by a temperature controller. The first and the second controllable switches are used for connection to the DC source, and the third and fourth switches are grounded with the possibility of switching from the third controllable switch over to the first controllable switch and from the fourth controllable switch over to the second controllable switch.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: December 25, 2018
    Assignee: OBSHCHESTVO S OGRANICHENNOY OTVETSTVENNOSTYU “KOMPANIYA RMT”
    Inventors: Semen Aleksandrovich Glyazer, Gennady Gyusamovich Gromov, Aleksei Leonardovich Ogryzko
  • Patent number: 10163888
    Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
  • Patent number: 10163826
    Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Matt E. Schwab, David J. Corisis, J. Michael Brooks
  • Patent number: 10157917
    Abstract: A semiconductor device is provided. The semiconductor device may include a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film. The gate electrode may include a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern. A height from the substrate to a lowest part of the first portion may be different than a height from the substrate to a lowest part of the second portion.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gun You, Se-Wan Park, Baik-Min Sung, Myung-Yoon Um
  • Patent number: 10157908
    Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Junjun Li, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 10156012
    Abstract: There is provided a cleaning method improving cleaning efficiency in a process container after an oxygen-containing film forming process is having performed, including: (a) supplying at least a hydrogen fluoride gas into the process container; and (b) supplying an alcohol into the process container in a state where supply of the hydrogen fluoride gas into the process container is stopped, wherein (a) and (b) are continuously performed without providing an intermittent period therebetween.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 18, 2018
    Assignees: KOKUSAI ELECTRIC CORPORATION, CENTRAL GLASS CO., LTD.
    Inventors: Kenji Kameda, Masaya Nagato, Akiou Kikuchi, Yuta Takeda, Kunihiro Yamauchi
  • Patent number: 10158003
    Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: December 18, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Zuoguang Liu, Ruilong Xie, Tenko Yamashita