Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

Abstract: The present invention is directed to provide a hydrophobized phosphor not susceptible to separation at the interface with sealing resins and, by using this hydrophobized phosphor, a light-emitting device having excellent long-term stability and little change in luminance and emission color over time. The hydrophobized phosphor is characterized in that it comprises phosphor particles represented by the general formula Si6-zAlzOzN8-z:Eu2+ (where z is larger than 0 and no more than 4.2); and a surface layer consisting of a hydrophobic substance deposited on the surfaces of the phosphor particles; wherein the hydrophobic substance consists of a long-chain fatty acid having 12 or more carbon atoms, a silicone oil having a viscosity of 1.5 Pa·s or less, or a combination thereof. The light-emitting device is characterized in that it comprises the hydrophobized phosphor and a light-emitting element.

Abstract: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.

Abstract: The use of a polymeric composition as an encapsulant in a photovoltaic module, said polymeric composition including a copolymer that comprises an ethylene monomer and a carboxylic acid vinyl ester comonomer, in particular an ethylene vinyl acetate copolymer, and the polymeric composition having a Brookfield viscosity measured at 120° C. of between 10,000 mPa·s and 25,000 mPa·s. Further, a method for encapsulating a photovoltaic module using this polymeric composition.

Abstract: A method for forming a light-emitting package structure provided with a predetermined view angle is provided. The method includes the steps of: disposing a flip chip on a carrier substrate; filling an underfill material between at least two electrodes of the flip chip for supporting the flip-chip; laser lifting-off a growing substrate from the flip chip for forming a thin film chip and exposing an epitaxial structure from the thin film chip; roughening the epitaxial structure exposed from the thin film chip; providing a view angle adjusting structure including a wavelength converting layer on the thin film chip, and selecting a predetermined view angle and achieving the predetermined view angle by adjusting the view angle adjusting structure according to a linear regression formula.

Abstract: The present application discloses a method of manufacturing a thin film transistor, including following steps: forming a gate electrode on the top surface of the substrate; depositing a gate insulating layer, a semiconductor material and an etching stop layer sequentially on the gate electrode; patterning the etching stop layer by a first mask to form a stopper; depositing a second metal layer; using a second mask and a photoresist to form a source electrode region, a drain electrode region and a channel region on the surface of the second metal layer; etching the periphery region of the source electrode region, the drain electrode region and the channel region to expose the gate insulating layer; removing the photoresist and etching the second metal layer within the channel, and form a source electrode and a drain electrode by the remaining second metal layer; and irradiating the bottom of the substrate.

Abstract: A method of forming a wrap around contact, includes forming a plurality of semiconductor layers on a plurality of fin structures, forming a sacrificial gate on the plurality of semiconductor layers, forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer, and forming a wrap around contact on the epitaxial layer.

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

Abstract: This application relates to MEMS devices, especially MEMS capacitive transducers and to processes for forming such MEMS transducer that provide increased robustness and resilience to acoustic shock. The application describes a MEMS transducer having a flexible membrane (101) supported relative to a first surface of a substrate (105) which has one or more cavities therein, e.g. to provide an acoustic volume. A stop structure (401, 402) is positioned so as to be contactable by the membrane when deflected so as to limit the amount of deflection of the membrane. The stop structure defines one or more openings to the one or more substrate cavities and comprises at least one narrow support element (401, 402) within or between said one or more openings. The stop structure thus limits the amount of membrane deflection, thus reducing the stress experienced at the edges and prevents the membrane from contacting a sharp edge of a substrate cavity.

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.

Abstract: The present invention provides a manufacturing method of a top gate thin-film transistor, which includes forming a reducing metal layer on an oxide semiconductor layer and applying laser annealing to reduce the oxide semiconductor layer that is covered with the reducing metal layer to conductors to respectively form a source contact zone and a drain contact zone, such that the source contact zone and the drain contact zone that have been reduced to conductors are used to respectively contact a source electrode and a drain electrode thereby greatly reducing the contact resistance of the source electrode and the drain electrode and improving the performance of a top gate thin-film transistor. The manufacturing process is simple.

Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.

Abstract: A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.

Abstract: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.

Abstract: A method for forming a light-emitting package structure provided with a predetermined view angle is provided. The method includes the steps of: disposing a flip chip on a carrier substrate; filling an underfill material between at least two electrodes of the flip chip for supporting the flip-chip; laser lifting-off a growing substrate from the flip chip for forming a thin film chip and exposing an epitaxial structure from the thin film chip; roughening the epitaxial structure exposed from the thin film chip; providing a view angle adjusting structure including a wavelength converting layer on the thin film chip, and selecting a predetermined view angle and achieving the predetermined view angle by adjusting the view angle adjusting structure according to a linear regression formula.

Abstract: An LED display module is disclosed. The LED display module includes: an active matrix substrate including a plurality of control units; a plurality of pairs of solder bumps arranged in a matrix on the active matrix substrate by transfer printing; a plurality of LED chips including pairs of electrodes connected to the corresponding plurality of pairs of solder bumps and arranged in a matrix on the active matrix substrate by transfer printing; grid barriers formed on the active matrix substrate to isolate the plurality of LED chips into individual chip units; and a multi-color cell layer including a plurality of color cells and aligned with the active matrix substrate such that the plurality of color cells match the plurality of LED chips in a one-to-one relationship. The plurality of color cells include first color cells, second color cells, and third color cells disposed consecutively in one direction.

Abstract: One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer.

Abstract: A method for forming a Boron doped metallic film, such as Titanium Boron Nitride, is disclosed. The method allows for creation of the metallic film with a high work function and low resistivity, while limiting the increase in effective oxide thickness. The method comprises a thin metallic layer deposition step as well as a Boron-based gas pulse step. The Boron-based gas pulse deposits Boron and allows for the removal of excess halogens within the metallic film. The steps may be repeated in order to achieve a desired thickness of the metallic film.

Abstract: The present disclosure relates to an ultra high density display having high aperture ratio.