Abstract: The invention relates to a plasma treatment device with a treatment chamber, at least one pair of microwave plasma sources and at least one voltage source. Each pair of microwave plasma sources consists of a first microwave plasma source and a second microwave plasma source, wherein the first and the second microwave plasma source each have a plasma source wall and, within this, a microwave coupling-in device and a plasma electrode. The first and the second microwave plasma source are arranged within the treatment chamber on the same side of one or more substrates to be processed and adjacently to one another. The plasma electrodes of the first microwave plasma source and the second microwave plasma source are electrically insulated from one another and electrically conductively connected to the at least one voltage source. Here, the at least one voltage source is suitable for supplying the plasma electrodes of the first and the second microwave plasma source with different potentials.

Abstract: A logic level shifter interface including a string of logic components communicating between a first power domain and a second power domain; a first string of resistive components connecting a first power rail of the first power domain to a first power rail of the second power domain and having a plurality of intermediate first power rails at nodes between adjacent resistive components of the first string of resistive components; and a second string of resistive components connecting a second power rail of the first power domain to a second power rail of the second power domain and having a plurality of intermediate second power rails at nodes between adjacent resistive components of the second string of resistive components, where at least one logic component is powered by an intermediate first power rail of the first string of resistive components and an intermediate second power rail of the second string of resistive components.

Abstract: A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.

Abstract: A method for generating atmospheric pressure cold plasma inside a hand-held unit discharges cold plasma with simultaneously different rf wavelengths and their harmonics. The unit includes an rf tuning network that is powered by a low-voltage power supply connected to a series of high-voltage coils and capacitors. The rf energy signal is transferred to a primary containment chamber and dispersed through an electrode plate network of various sizes and thicknesses to create multiple frequencies. Helium gas is introduced into the first primary containment chamber, where electron separation is initiated. The energized gas flows into a secondary magnetic compression chamber, where a balanced frequency network grid with capacitance creates the final electron separation, which is inverted magnetically and exits through an orifice with a nozzle. The cold plasma thus generated has been shown to be capable of accelerating a healing process in flesh wounds on animal laboratory specimens.

Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal.

Abstract: The present invention discloses a universal LED tube including a metal pin, an automatic dividing frequency network, a high-frequency driver, a low-frequency driver, a isolation circuit and a LED lighting set. The universal LED tube has the advantages of strong universality and high level of safety.

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

Abstract: A method and apparatus for reducing dynamic switching current in high speed logic. The apparatus may include a CMOS logic circuit, which in turn includes an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. A gate of the NMOS FinFET is connected to a gate of the first PMOS FinFET, a drain of the NMOS FinFET is connected to a drain of the first PMOS FinFET, and the second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between a source and the drain of the first PMOS FinFET. In one embodiment, the second PMOS FinFET is contained in and positioned at an edge of a cell that also contains the first PMOS FinFET and the NMOS FinFET.

Abstract: A quantum controller comprises a first quantum control pulse generation circuit and a second quantum control pulse generation circuit. The first quantum control pulse generation circuit and a second quantum control pulse generation circuit are operable to operate asynchronously during some time intervals of a quantum algorithm and synchronously during other time intervals of the quantum algorithm.

Abstract: Systems and methods utilizing successive, axially symmetric acceleration and adiabatic compression stages to heat and accelerate two compact tori towards each other and ultimately collide and compress the compact tori within a central chamber. Alternatively, systems and methods utilizing successive, axially asymmetric acceleration and adiabatic compression stages to heat and accelerate a first compact toroid towards and position within a central chamber and to heat and accelerate a second compact toroid towards the central chamber and ultimately collide and merge the first and second compact toroids and compress the compact merge tori within the central chamber.

Abstract: An automated luminaire and method are presented. The luminaire includes a light source, an ellipsoidal reflector, an optical device, and a controller. The ellipsoidal reflector produces an emitted light beam and moves along an optical axis. The optical device receives the emitted light beam and produces either a modified light beam or an unmodified light beam. The controller determines whether the optical device is producing the modified or unmodified light beam. If the optical device is producing the modified light beam, the controller automatically moves the ellipsoidal reflector to a selected position to reduce an effect on the optical device of a hotspot in the emitted light beam. The controller may move the ellipsoidal reflector to a selected position relative to the light source in response to determining that the optical device is producing the modified light beam.

Abstract: There is disclosed in one example an integrated circuit, including: a network protocol circuit to provide communication via a network protocol; a network communication terminal having a configurable impedance; and a control circuit including a control input port, and circuitry to adjust the impedance of the network communication terminal responsive to an input signal.

Abstract: A plasma chamber is provided to increase conductance within the plasma chamber and to increase uniformity of the conductance. A radio frequency (RF) path for supplying power to the plasma chamber is symmetric with respect to a center axis of the plasma chamber. Moreover, pumps used to remove materials from the plasma chamber are located symmetric with respect to the center axis. The symmetric arrangements of the RF paths and the pumps facilitate an increase in conductance uniformity within the plasma chamber.

Abstract: Various embodiments of a light source driver are disclosed. In one embodiment, the light source driver may have a driving transistor coupled directly to at least one light source without having additional switches such that the light source driver may be operated with a low voltage supply. Optionally, the light source drivers may have a bypassing circuit configured to reduce power consumption, and peaking current generator configured to speed up the turn on time of the at least one light source. At least some of the circuits, and block diagrams disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.

Abstract: A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.

Abstract: A voltage translator having first and second one-shots shifts a voltage level of a first voltage signal to generate a second voltage signal, and vice-versa. The first one-shot generates a first driver signal when the first voltage signal goes from low to high based on a time duration for which the first voltage signal remains high. The second voltage signal is generated based on the first driver signal. Similarly, the second one-shot generates the first voltage signal when the second voltage signal goes from a low to high based on a time duration for which the second voltage signal remains high.

Abstract: The output driving circuit include a pull-down driver, an input/output (IO) control logic, a gate control logic, and an inverter. The pull-down driver includes first, second, and third transistors that are sequentially coupled between a pad and a ground node. The IO control logic is configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor. The inverter is configured to invert the enable signal and transfer an inverted enable signal to the gate control logic. Therefore, the reliability of the output driving circuit can be improved.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate external port measurement of qubit port responses are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analysis component that can analyze responses of a multi-mode readout device coupled to a qubit. The computer executable components can further comprise an assignment component that can assign a readout state of the qubit based on the responses. In some embodiments, the multi-mode readout device can be electrically coupled to at least one of the qubit or an environment of the qubit based on a defined electrical coupling value.

Abstract: Systems and methods for tuning to reduce reflected power in multiple states are described. The methods include determining values of one or more parameters of an impedance matching circuit so that reflected power is reduced for multiple states. Such a reduction in the reflected power increases a life of a radio frequency generator coupled to the impedance matching circuit while simultaneously processing a substrate using the multiple states.