Abstract: In a cleaning method according to an exemplary embodiment, a plasma is formed from a cleaning gas in a chamber of a plasma processing apparatus. A focus ring is mounted on a substrate support in the chamber to extend around a central axis of the chamber. While the plasma is formed, a magnetic field distribution is formed in the chamber by an electromagnet. The magnetic field distribution has a maximum horizontal component in a location on the focus ring or a location outside the focus ring in a radial direction with respect to the central axis.

Abstract: A repeating setpoint generator module selectively varies a setpoint for an output parameter according to a predetermined pattern that repeats during successive time intervals. A closed-loop module, during a first one of the time intervals, generates N closed-loop values based on N differences between (i) N values of the setpoint at N times during the first one of the time intervals and (ii) N measurements of the output parameter at the N times during the first one of the time intervals, respectively. An adjusting module, during the first one of the time intervals, generates N adjustment values based on N differences between (i) N values of the setpoint at the N times during a second one of the time intervals and (ii) N measurements of the output parameter at the N times during the second one of the time intervals, respectively.

Abstract: Disclosed are methods and devices suitable for producing an electron beam.

Abstract: The present invention relates to a projecting light fixture comprising at least one LED generating light beam and a projecting system positioned configured to project the light beam along an optical axis. A beam shaping object is arranged between the LED and the projecting system and comprises a least two different beam shaping patterns, which can be arranged in the source light beam upon rotation of the beam shaping object in relation to the light beam. An actuator is configured to continuously rotate the beam shaping object in relation to the source light beam in order to alternately arrange the beam shaping patterns in the light beam. The projecting light fixture comprises a synchronizer providing a synchronizing signal indicative of: the rotation speed and/or the angular position of the beam shaping object; the position of beam shaping patters in relation to the light beam. Where a controller is configured to toggle the LED between a LED on-period and a LED off-period based on the synchronizing signal.

Abstract: An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.

Abstract: A power conversion apparatus includes positive-side and negative-side switching elements, positive-side and negative-side gate drive circuits, and a gate signal controller. The positive-side switching element is disposed between a positive-side direct-current bus and an output node. The negative-side switching element is disposed between a negative-side direct-current bus and the output node. The positive-side and negative-side gate drive circuit are configured to turn on and off the positive-side and negative-side switching elements, respectively. The gate signal controller is configured to transmit to the positive-side and negative-side gate drive circuits gate signals to instruct turning on and off the positive-side and negative-side switching elements.

Abstract: Plasma processing systems and methods are disclosed. The plasma processing system includes a high-frequency generator configured to deliver power to a plasma chamber and a low-frequency generator configured to deliver power to the plasma chamber. A filter is coupled between the plasma chamber and the high-frequency generator, and the filter suppresses mixing products of high frequencies produced by the high-frequency generator and low frequencies produced by the low-frequency generator.

Abstract: A sensor fixed atop a structure, The sensor including an image-capturing device configured to collect image data and an electronic processing device. The electronic processing device is configured to receive, via the image-capturing device, the image data, determine a wobble state value of the image data, filter the image data when the wobble state value is approximately equal to a first wobble state threshold, perform a first timeout for a first predetermined time period when the wobble state value is approximately equal to a second wobble state threshold, and increment the first timeout to a second timeout for a second predetermined time period when the wobble state value is approximately equal to the second wobble state threshold following the first timeout.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: The invention relates to high-frequency amplifier apparatuses suitable for generating power outputs of at least 1 kW at frequencies of at least 2 MHz. The apparatuses include two LDMOS transistors each connected by their source connection to ground. The transistors can have the same design and can be arranged in an assembly (package). The apparatus also includes a circuit board lying flat against a metallic cooling plate and connected to the cooling plate, which can be connected to ground, and the assembly is arranged on or against the circuit board. The apparatuses have a power transformer, whose primary winding is connected to the drain connections of the transistors, and a signal transmitter. A secondary winding of the signal transmitter is connected to the gate connections of the two transistors. Each of the gate connections is connected to ground via at least one voltage-limiting structural element.

Abstract: A control unit controls a bidirectional switch so as to turn the switch from ON to OFF when an amount of time, varying according to a lighting level, passes since a starting point of a half cycle of an AC voltage. When a voltage between both terminals of a capacitive element, connected to a control terminal of the bidirectional switch, becomes equal to or greater than a threshold voltage, the bidirectional switch turns from OFF to ON A first charging/discharging regulator circuit and a second charging/discharging regulator circuit each make a rate of fall of the voltage between both of the terminals of the capacitive element when the bidirectional switch turns from ON to OFF lower than a rate of rise of the voltage between both of the terminals of the capacitive element when the bidirectional switch turns from OFF to ON.

Abstract: Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.

Abstract: An object of the present invention is to reduce a chip area of the high-side driver circuit. A high-side driver circuit of the present invention is a high-side driver circuit in which a first potential is set as a power supply potential, which includes a constant voltage circuit configured to operate with a second potential as a reference potential, and generate, from the first potential, a third potential which is lower than the first potential and higher than the second potential, a logic circuit configured to operate with the third potential as a reference potential, a level shift circuit configured to shift the reference potential of the output signal of the logic circuit from the third potential to the second potential, and a driver circuit in which the second potential is set as a reference potential, and configured to drive a switching element by the output signal.

Abstract: Systems and methods for monitoring operating conditions of a programmable device are disclosed. The system may include a root monitor configured to generate a reference voltage, a plurality of sensors distributed across the device, and a plurality of satellite monitors distributed across the device. Each of the satellite monitors may be coupled to a corresponding sensor via a local interconnect, and may be configured to convert analog signals generated by the sensor into digital data indicative of one or more operating conditions of an associated circuit. In some implementations, each satellite monitor may include a circuit to store a local reference voltage, an analog-to-digital converter (ADC) to convert the analog signals into digital codes, a calibration circuit to generate a correction factor indicative of errors in the digital codes, and a correction circuit to correct the digital codes based on the correction factor.

Abstract: An impedance matching system is provided. The impedance matching system includes: an impedance matching device arranged between a radio frequency (RF) power supply and a reaction chamber, adapted to connect the RF power supply to the reaction chamber through a switch, and configured to automatically perform an impedance matching on an output impedance of the RF power supply and an input impedance of the impedance matching device; the switch and a load circuit, the switch being configured to enable the RF power supply to be selectively connected to the reaction chamber or to the load circuit; and a control unit configured to control the switch to connect the RF power supply to the reaction chamber or connect the RF power supply to the load circuit according to a preset timing sequence. The impedance matching device is configured to convert a continuous wave output of the RF power supply into a pulse output according to the preset timing sequence, and provide the pulse output to the reaction chamber.

Abstract: A PUF code generation apparatus that includes a reference generator, a PUF information generation and storage array, a sensing amplifier and a writing driver is introduced. The PUF information generation and storage array includes a plurality of first memory cells each including a PUF information providing element and a PUF information storage element. The sensing amplifier compares a plurality of first electrical values read from the PUF information providing elements to a reference generated from the reference generator to generate a plurality of PUF information. The writing driver performs a write-back operation on the PUF information storage elements according to the plurality of PUF information. The sensing amplifier reads a plurality of second electrical values of the PUF information storage elements to generate a sensing result and output a PUF code according to the sensing result.

Abstract: A broadband radiation source is disclosed. The system may include a plasma containment vessel configured to receive laser radiation from a pump source to sustain a plasma within gas flowed through the plasma containment vessel. The plasma containment vessel may be further configured to transmit at least a portion of broadband radiation emitted by the plasma. The system may also include a recirculation gas loop fluidically coupled to the plasma containment vessel. The recirculation gas loop may be configured to transport heated gas from an outlet of the plasma containment vessel, and further configured to transport cooled gas to an inlet of the plasma containment vessel.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.

Abstract: According to an embodiment, in a CEM assembly and the like, it is possible to reduce a size of a voltage supply circuit configured to stabilize a voltage to be applied to a channel electron multiplier. The CEM assembly includes a CEM and a voltage supply circuit. The CEM includes an input electrode, a multiplication channel, and an output electrode. The voltage supply circuit includes a power source unit and a constant voltage generation unit. A potential of an input electrode A is set by an electromotive force generated by the power source unit. The constant voltage generation unit includes a constant voltage supply unit configured to cause voltage drop. A target potential set at an output-side reference node is maintained by the voltage drop of the constant voltage supply unit.