Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.

Abstract: A semiconductor device including: a first layer including a first memory cell, the first memory cell including a first transistor; a second layer including a second memory cell, the second memory cell including a second transistor; a periphery layer including a memory peripherals transistor, the periphery layer is disposed underneath the first layer; a memory including at least the first memory cell and the second memory cell, where the second memory cell overlays the first memory cell, where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where a peripherals circuit includes the memory peripherals transistor and controls the memory; a first external connections underlying the periphery layer, the first external connections includes connections from the device to a first external device; and a second external connections overlying the second layer, the second external connections includes connections from the dev

Abstract: An off-leakage current of a photodiode is reduced in a photoelectric conversion device. A photoelectric conversion device (100) includes: an oxide semiconductor layer (5) provided on a substrate (1); a passivation film (6) and a planarizing film (7) which are stacked on the oxide semiconductor layer; and a photodiode (9) including a lower electrode (91), a photoelectric conversion layer (92), and an upper electrode (93). The lower electrode is connected to a source electrode (4) via a contact hole provided in the passivation film and the planarizing film. No photoelectric conversion layer is provided directly above the contact hole.

Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.

Abstract: A manufacturing method of a LTPS-TFT is provided, including: providing a substrate, sequentially forming a buffer layer, a low temperature poly-silicon layer, a source contact region, a drain contact region, a gate insulator layer, a gate layer, and a dielectric layer on the substrate, respectively forming a first and a second contact holes through the dielectric layer and the gate insulator layer by dry etching to expose the source and the drain contact regions; and on the dielectric layer, forming a source electrode to contact the source contact region through the first contact hole and a drain electrode to contact the drain contact region through the second contact hole. A LTPS-TFT and an array substrate are also provided.

Abstract: A semiconductor structure includes a semiconductor device located over a substrate, a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer, and at least one second dielectric material layer overlying the semiconductor device, and interconnect structures including metallic lines and metallic vias and embedded within the dielectric layer stack. The interconnect structures also include a metal silicide portion that directly contacts the silicon nitride layer. A combination of the silicon nitride layer and the metal silicide portion provides a continuous hydrogen barrier structure that is vertically spaced from the top surface of the semiconductor device.

Abstract: A heat sink can be attached to a heat-producing electronic device by aligning an adhesive material to a surface of the heat sink, applying the adhesive material to the surface to form an outer perimeter and applying, within the outer perimeter, a thermally conductive material to the surface. The surface of the heat sink and a surface of the heat-producing electronic device can then be aligned, and the heat sink can be assembled to the heat-producing electronic device by bringing the heat-producing electronic device surface into contact with the adhesive material. The heat sink can then be affixed to the heat-producing electronic device by applying a compressive force to the assembly to activate the adhesive material.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

Abstract: A component with a semiconductor body, a first metal layer and a second metal layer is disclosed. The first metal layer is arranged between the semiconductor body and the second metal layer. The semiconductor body has a first semiconductor layer, a second semiconductor layer, and an active layer. The component has a plated-through hole, which extends through the second semiconductor layer and the active layer for the electrical contacting of the first semiconductor layer. The second metal layer has a first subregion, and a second subregion, spaced apart laterally from the first subregion by an intermediate space. The first subregion is electrically connected to the plated-through hole and is assigned to a first electrical polarity of the component. In plan view, the first metal layer laterally completely bridges the intermediate space and is assigned to a second electrical polarity of the component which differs from the first electrical polarity.

Abstract: The present disclosure provides thermal interface materials that are useful in transferring heat from heat generating electronic devices, such as computer chips, to heat dissipating structures, such as heat spreaders and heat sinks. The thermal interface material also includes a coloring agent selected from the group consisting of: an iron based inorganic pigment; and an organic pigment.

Abstract: A cobalt contact includes a dual silicide barrier layer. The barrier layer, which may be formed in situ, includes silicides of titanium and cobalt, and provides an effective adhesion layer between the cobalt contact and a conductive device region such as the source/drain junction of a semiconductor device, eliminating void formation during a metal anneal.

Abstract: A heat sink can be attached to a heat-producing electronic device by aligning an adhesive material to a surface of the heat sink, applying the adhesive material to the surface to form an outer perimeter and applying, within the outer perimeter, a thermally conductive material to the surface. The surface of the heat sink and a surface of the heat-producing electronic device can then be aligned, and the heat sink can be assembled to the heat-producing electronic device by bringing the heat-producing electronic device surface into contact with the adhesive material. The heat sink can then be affixed to the heat-producing electronic device by applying a compressive force to the assembly to activate the adhesive material.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.

Abstract: Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, and a device die formed over the package component. The device die includes a device substrate and a conductive pad over the device substrate, and the device die has a first height. The package structure also includes a dummy die formed over the package component and adjacent to the device die, and the dummy die has a second height smaller than the first height.

Abstract: In a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy. The proportion of the thickness of the electroless nickel-phosphorus plating layer formed on the front-side electrode with respect to the thickness of the electroless nickel-phosphorus plating layer formed on the back-side electrode is in a range of 1.0 to 3.5. The semiconductor element of the present invention allows the occurrence of voids inside solder during mounting by soldering to be prevented.