Abstract: An addition curable type silicone resin composition includes (a) an organopolysiloxane having an alkenyl group bonded to a silicon atom, (b) an organopolysiloxane represented by the formula, (R1R22SiO1/2)m(R1R2SiO2/2)n(R22SiO2/2)p(R1SiO3/2)q(R2(OR3)SiO2/2)r(SiO4/2)s, (c) an organohydrogen polysiloxane represented by R4aHbSiO(4-a-b)/2, (d) a platinum group metal catalyst, and (e) a polyorganometallosiloxane containing an Si—O—Ce bond, and an Si—O—Ti bond, and contents of Ce and Ti of which are each 50 to 5,000 ppm, which cures by heating. According to this constitution, it is provided an addition curable type silicone resin composition which can provide a cured product excellent in transparency, and less change in hardness and weight loss under high temperature conditions.

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Abstract: An optically readable chip ID is provided to an imprintable material that is formed as a last level of an integrated circuit (IC) chip using nanoimprint lithography. The nanoimprint lithography process provides an array of indentations into the imprintable material that is typically arranged in a hexadecimal pattern. The hexadecimal pattern includes one or more optically readable characters which combine to encode chip location identification data. The chip location identification data identifies a unique location of the product chip on a wafer prior to dicing.

Abstract: The present disclosure relates to a solid-state image sensing device, a manufacturing method, and an electronic apparatus, in which surface roughness on a wiring surface can be suppressed. In redistribution layer forming processing, a Ti/Cu film corresponds to a barrier layer and a seed layer is formed by Ti/Cu sputtering after opening a through-silicon via. At this point, actually, degassing heating, reverse sputtering, Ti deposition, and Seed-Cu deposition are sequentially performed. As a method of depositing a Seed-Cu film having high crystallinity in deposition of the Seed-Cu film, performing deposition by increasing a substrate temperature to a high temperature is one method, and the Seed-Cu film of Cu(111)/(200) is formed by performing deposition at the substrate temperature of 60 degrees or more, and Cu haze are suppressed. The present disclosure can be applied to a CMOS solid-state image sensing device used as an imaging device such as a camera.

Abstract: A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.

Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

Abstract: This disclosure provides a test circuit for a display panel and a display device. The test circuit for the display panel comprises one or more shorting bars, a plurality of signal lines, and a switch circuit connected with the shorting bars and the signal lines. The switch circuit establishes a connection between the signal lines and a corresponding shorting bar when the display panel is tested, and the switch circuit cuts off the connection between the signal lines and the corresponding shorting bar when the display panel is not tested.

Abstract: A flexible array substrate includes a substrate, a gate electrode and a scan line disposed on the substrate, and a first insulation layer disposed on the gate electrode and the scan line. The array substrate further includes an electrically conductive channel disposed on the first insulation layer; a source electrode; a drain electrode; and a data line disposed on the electrically conductive channel; a second insulation layer disposed on the source electrode; the drain electrode; and the data line; and a pixel electrode disposed on the second insulation layer.

Abstract: A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.

Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the semiconductor chip, and a projecting portion which projects in a first direction from the supporting portion. A second lead extends in a second direction non-parallel with the first direction, and one or more third leads extends in the second direction, such that a line extending in a third direction perpendicular to the first direction passes through the second lead and the one or more third leads. The second lead includes a first portion and a second portion, the first portion having a width larger than the second portion, the first portion having one side parallel to the first direction, and the first portion located between the second portion and the first lead.

Abstract: An electronic component housing package includes an insulating substrate having a first principal face and a second principal face opposing the first principal face; external connection conductors provided on the second principal face; and connection conductors provided so as to extend from outer peripheral ends of the external connection conductors to outer peripheral ends of the insulating substrate, respectively. The connection conductors are provided so as to be curved convexly toward a first principal face side over a range from the outer peripheral ends of the external connection conductors to the outer peripheral ends of the insulating substrate in a vertical cross-sectional view of the electronic component housing package and so that a distance from each of the connection conductors to the second principal face is gradually increased in a thickness direction of the insulating substrate. Insulating bodies are provided so as to cover the connection conductors, respectively.

Abstract: A first substrate has a first mesa structure that protrudes from a first bonding-side planar surface. A first metal pad structure is embedded within the first mesa structure. A second substrate has a first recess cavity that is recessed from a second bonding-side planar surface. A second metal pad structure is located at a recessed region of the first recess cavity. The first bonding-side planar surface and the second bonding-side planar surface are brought into physical contact with each other, while the first mesa structure is disposed within a volume of the first recess cavity by self-alignment. A gap is provided between the first metal pad structure and the second metal pad structure within a volume of the first recess cavity. A metal connection pad is formed by selectively growing a third metallic material from the first metal pad structure and the second metal pad structure.

Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.

Abstract: A wrap-around contact integration scheme is described that includes sidewall protection during contact formation. A substrate processing method includes providing a substrate containing a raised contact in a first dielectric film, and a second dielectric film on the first dielectric film, where the second dielectric film has a recessed feature with a sidewall and a bottom portion above the raised contact. The method further includes depositing a conformal film on the sidewall and on the bottom portion of the recessed feature, removing the conformal film from the bottom portion in a first anisotropic etching process, where the remaining conformal film forms a protection film on the sidewall and defines a width of the recessed feature, and forming a cavity containing the raised contact in an isotropic etching process, where a width of the cavity is greater than the width of the recessed feature.

Abstract: A light emitting apparatus that includes at least one kind of light emitting elements of which the number is one or more, and a phosphor that is excited by output light of the light emitting element. In a case where all light emitting elements mounted before the phosphor is mounted in the light emitting apparatus emit light, the light emitting apparatus has a peak wavelength of output light in a first wavelength region of 440 nm or longer and shorter than 460 nm, and has a peak wavelength of output light in a second wavelength region of 460 nm to 490 nm.

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.

Abstract: An image sensor includes a separation impurity layer in a semiconductor layer and defining a photoelectric conversion region and a readout circuit region, a photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer, a floating diffusion region spaced apart from the photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region, a transfer gate electrode between the photoelectric conversion layer and the floating diffusion region, and impurity regions in the semiconductor layer of the readout circuit region. When the photoelectric conversion layer is integrated with photo-charges, the separation impurity layer has a first potential level around the photoelectric conversion layer and a second potential level on a portion between the photoelectric conversion layer and the impurity regions of the readout circuit region. The second potential level is greater than the first potential level.