Patents Examined by Alexander Oscar Williams
  • Semiconductor memory device having dummy conductive patterns on interconnection
    Patent number: 8759979
    Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: June 24, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jang Uk Lee
  • Solder joints with enhanced electromigration resistance
    Patent number: 8759974
    Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Mengzhi Pang, Pilin Liu, Charavanakumara Gurumurthy
  • Method for processing semiconductors using a combination of electron beam and optical lithography
    Patent number: 8754421
    Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: June 17, 2014
    Assignee: Raytheon Company
    Inventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
  • MEMS device with simplified electrical conducting paths
    Patent number: 8754529
    Abstract: A MEMS device comprises a substrate for manufacturing a moving MEMS component is divided into two electrically isolated conducting regions to allow the moving MEMS component and a circuit disposed on its surface to connect electrically with another substrate below respectively through their corresponding conducting regions, thereby the electrical conducting paths and manufacturing process can be simplified.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 17, 2014
    Assignee: Miradia, Inc.
    Inventors: Yu-Hao Chien, Hua-Shu Wu, Shih-Yung Chung, Li-Tien Tseng, Yu-Te Yeh
  • Semiconductor device with resin mold
    Patent number: 8749055
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 10, 2014
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Semiconductor package having an anti-contact layer
    Patent number: 8742577
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 3, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young-kun Jee, Sun-kyoung Seo, Sang-wook Park, Ji-hwan Hwang
  • Maintaining alignment in a multi-chip module using a compressible structure
    Patent number: 8742576
    Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 3, 2014
    Assignee: Oracle International Corporation
    Inventors: Hiren D. Thacker, Hyung Suk Yang, Ivan Shubin, John E. Cunningham
  • Multi-level vertical plug formation with stop layers of increasing thicknesses
    Patent number: 8736069
    Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 27, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chiajung Chiu, Guanru Lee
  • Method and system for controlling a maximum signal level output to headphones coupled to a wireless device
    Patent number: 8718287
    Abstract: A method for controlling a maximum signal level output to headphones of a wireless device is provided. The method includes: determining an impedance of the headphones; determining a carrier specific maximum signal level for headphones having the impedance; and, adjusting an audio amplifier of the wireless device coupled to the headphones to restrict the maximum signal level output to the headphones to the carrier specific maximum signal level.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 6, 2014
    Assignee: BlackBerry Limited
    Inventor: Cyril Martin
  • Stacked semiconductor package including connections electrically connecting first and second semiconductor packages
    Patent number: 8716872
    Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Su-chang Lee
  • Big via structure
    Patent number: 8716871
    Abstract: A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Uway Tseng, Shu-Hui Su
  • Micro-electro mechanical systems (MEMS) having outgasing prevention structures and methods of forming the same
    Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Under bump passive components in wafer level packaging
    Patent number: 8710658
    Abstract: Under bump passive structures, such as capacitors and inductors, may be formed using the post-processing layers in wafer level packaging. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: April 29, 2014
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Zaid Aboush
  • Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer
    Patent number: 8710669
    Abstract: A semiconductor device includes a core substrate, and at least one insulating layer and at least one wiring layer that are disposed on a first surface and a second, opposite surface of the substrate. The semiconductor device includes a via disposed in the insulating layer and in the core substrate, and which connects the wiring layers to one another. The semiconductor device includes a semiconductor element mounted on the first surface, forming an electrode terminal that faces up. The semiconductor device includes a connecting portion that penetrates the insulating layer and directly connects the electrode terminal of the semiconductor element and the wiring layer on the first surface. A minimum wiring pitch of this wiring that of any wiring layer on the second surface.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: April 29, 2014
    Assignee: NEC Corporation
    Inventors: Kentaro Mori, Yoshiki Nakashima, Daisuke Ohshima, Katsumi Kikuchi, Shintaro Yamamichi
  • Chip on chip semiconductor device including an underfill layer having a resin containing an amine-based curing agent
    Patent number: 8710653
    Abstract: A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Fukuda, Hiroshi Watabe
  • Multi-chip package with a supporting member and method of manufacturing the same
    Patent number: 8710677
    Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion.
    Type: Grant
    Filed: August 4, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jin Lee, Woo-Dong Lee
  • Isolation rings for blocking the interface between package components and the respective molding compound
    Patent number: 8710681
    Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
  • Hybrid interconnect scheme including aluminum metal line in low-k dielectric
    Patent number: 8710660
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Die packages and systems having the die packages
    Patent number: 8710655
    Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Joong Kim, Jang Seok Choi, Chul-Hwan Choo
  • Distributed audio system
    Patent number: 8705756
    Abstract: An apparatus comprising a housing, a speaker, and an amplifier. The speaker may be mounted within the housing. A concave portion may be implemented in the housing and may be configured to hold a transformer. An amplifier may be implemented within the housing and may be configured to receive power through a connection to the transformer.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Sound Merchandising, Inc.
    Inventors: Jeffrey S. O'Shea, Dennis M. O'Shea