Patents Examined by Alexander Oscar Williams
  • Conductive bump structure with a plurality of metal layers
    Patent number: 8952537
    Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
  • Packaging method using solder coating ball and package having solder pattern including metal pattern
    Patent number: 8952531
    Abstract: A packaging method comprises steps of forming a plurality of pads and another circuit pattern on a substrate, forming a second dry film pattern including opening exposing the pad, mounting a solder coating ball in the opening of the second dry film pattern, performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern, delaminating the second dry film pattern, and forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Won Choi, Yon Ho You
  • Semiconductor device with conductive layer over substrate with vents to channel bump material and reduce interconnect voids
    Patent number: 8952529
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JaeHyun Lee, SunJae Kim, JoongGi Kim
  • In situ-built pin-grid arrays for coreless substrates, and methods of making same
    Patent number: 8952540
    Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Semiconductor package and manufacturing method
    Patent number: 8941230
    Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Kyozuka, Akihiko Tateiwa, Yuji Kunimoto, Jun Furuichi
  • Semiconductor device with conductive vias
    Patent number: 8937387
    Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Hau Huang, Ying-Te Ou
  • Lead frame assembly, LED package and LED light bar
    Patent number: 8933481
    Abstract: A lead frame assembly includes a surrounding frame and a plurality of lead frame sets arranged in a matrix. Each lead frame set includes spaced-apart first and second lead frames and a connecting structure interconnecting one of the lead frame sets to an adjacent lead frame set. Each lead frame set is further connected to the surrounding frame through the connecting structure thereof. A plurality of insulated bars are spacedly formed on a lead frame panel. Each insulated bar covers a corresponding row of the lead frame sets and exposes bottom surfaces of the first and second lead frames. Each insulated bar further covers portions of the surrounding frame that are adjacent to two opposite outermost ones of the lead frame sets.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: January 13, 2015
    Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.
    Inventors: Chiou-Yueh Wang, Chen-Hsiu Lin, Shih-Chang Hsu
  • Semiconductor module and cooling unit
    Patent number: 8933557
    Abstract: A semiconductor module including a cooling unit by which a fine cooling effect is obtained is provided. A plurality of cooling flow paths (21c) which communicate with both of a refrigerant introduction flow path which extends from a refrigerant introduction inlet and a refrigerant discharge flow path which extends to a refrigerant discharge outlet are arranged in parallel with one another in a cooling unit (20). Fins (22) are arranged in each cooling flow path (21c). Semiconductor elements (32) and (33) are arranged over the cooling unit (20) so that the semiconductor elements (32) and (33) are thermally connected to the fins (22). By doing so, a semiconductor module (10) is formed. Heat generated by the semiconductor elements (32) and (33) is conducted to the fins (22) arranged in each cooling flow path (21c) and is removed by a refrigerant which flows along each cooling flow path (21c).
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: January 13, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiromichi Gohara, Akira Morozumi, Keiichi Higuchi
  • Electronic assembly with improved thermal management
    Patent number: 8933546
    Abstract: An electronic assembly includes a leadframe (2), a semiconductor component (3), and an electrically conductive connecting element (4) made of a composite material (5). The connecting element (4) has a solderable metallization (6) on the composite material (5) on a surface that is directed towards the semiconductor component (3). A thermal conductivity of the composite material (5) of the connecting element (4) is greater than a thermal conductivity of the semiconductor component (3) and less than a thermal conductivity of the leadframe (2). The connecting element (4) is provided only locally in the region of the semiconductor component (3).
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: January 13, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Paeivi Lehtonen, Thomas Kaden, Denis Gugel, Thomas Suenner, Tim Behrens
  • Lead frame including an insulating resin layer entirely covering lead surface, and semiconductor device including the same
    Patent number: 8928130
    Abstract: A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Kobayashi, Hiroshi Shimizu, Toshiyuki Okabe, Yasuyuki Kimura, Kazutaka Kobayashi
  • Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure
    Patent number: 8922008
    Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Yun Myung, Yong-Hwan Kwon, Jong-Bo Shim, Moon-Gi Cho
  • Insulated bump bonding
    Patent number: 8921986
    Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Roger Melcher
  • Mounting structure of electronic component with joining portions and method of manufacturing the same
    Patent number: 8922011
    Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Takatoshi Osumi, Daisuke Sakurai
  • Package-on-package (PoP) structure including stud bulbs and method
    Patent number: 8912651
    Abstract: Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng
  • Semiconductor device having alignment mark
    Patent number: 8912671
    Abstract: A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: December 16, 2014
    Assignees: Himax Technologies Limited, Himax Semiconductor, Inc.
    Inventors: Po-Yang Tsai, Chan-Liang Wu
  • Copper ball bond features and structure
    Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Nonvolatile memory devices having a three dimensional structure
    Patent number: 8896123
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Semiconductor device bonded by an anisotropic conductive film
    Patent number: 8896117
    Abstract: A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a conductive adhesive layer and an insulating adhesive layer stacked thereon, an amount of reactive monomers in the conductive adhesive layer being higher than an amount of reactive monomers in the insulating adhesive layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 25, 2014
    Assignee: Cheil Industries, Inc.
    Inventors: Youn Jo Ko, Jin Kyu Kim, Dong Seon Uh, Kil Yong Lee, Jang Hyun Cho
  • Three-dimensional integrated circuit
    Patent number: 8890303
    Abstract: A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 18, 2014
    Assignee: National Chiao Tung University
    Inventors: An-Nan Tan, Hung-Ming Chen
  • Substrate structure with through vias
    Patent number: 8878367
    Abstract: A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: November 4, 2014
    Assignee: Xintec Inc.
    Inventors: Chia-Sheng Lin, Chien-Hui Chen, Bing-Siang Chen, Tzu-Hsiang Hung