Abstract: A storage controller and method are provided. The storage controller includes control sections including storage sections into which data transmitted from a host unit is cached, one of the control sections being a main control section which controls firmware update in the control sections. The main control section includes an instruction updater sending an update instruction to a sub control section in the control sections in which firmware is to be updated, and an area instructor requesting the sub control section to transmit area information, the sub control section including an area information obtainer obtaining, according to the instruction from the area instructor and an area information transmitter transmitting to the area instructor; and an area setter setting the location of the cache area in the storage section on the basis of the instruction.

Abstract: System and method for configuring a portable device. The portable device includes a serial bus hub, one or more processors coupled to the serial bus hub via a serial bus, and a flash memory coupled to the serial bus hub via the serial bus. A degraded signal is received to a serial bus hub included in the portable device via a serial bus, where the degraded signal includes code to be written to the flash memory to initialize or update firmware for the portable device. The serial bus hub restores the degraded signal, thereby generating a restored signal, and sends the restored signal to at least one of the one or more processors to initialize or update the firmware in the flash memory for the portable device.

Abstract: A volume migration method for causing to carry out a migration from a first volume manager to a second volume, includes: by causing the first volume manager to carry out actual accesses, obtaining information of correspondence, by the first volume manager, between logical volume offsets and physical blocks on a physical medium; judging, based on the obtained information of the correspondence, whether or not an exceptional data layout is carried out; and when it is judged that the exceptional data layout is not carried out, updating only a header area on the physical medium for the second volume manager. Incidentally, the aforementioned obtaining is carried out by using a program module for blocking access by the first volume manager to the physical medium. Thus, when only the header area is updated after it is confirmed the exceptional data layout is not made, the high-speed volume migration becomes possible.

Abstract: A method, computer program product, and computing system for identifying a low-write-frequency portion of a solid-state storage device. If it is determined that the low-write-frequency portion is of sufficient size to function as over-provisioning space for the solid-state storage device, the low-write-frequency portion is utilized as over-provisioning space.

Abstract: An image input and output system is provided in which a common operation screen for a plurality of image output devices having different attributes is displayed. Based on attribute information of each of printers, the server generates a signal for generating an operation screen, and transmits the signal to the scanner. At the scanner, image data is inputted, and a common operation screen, which is generated based on the signal for generating the operation screen, is displayed on a display panel. When information designating the printer and information relating to an output format of an image is inputted from the display panel, the inputted information and the image data are transmitted to the server. The server transmits, to a designated printer, the image data and the information relating to the output format of the image, which are transmitted from the scanner, and images are outputted.

Abstract: Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units (7), to interpret that control information and take appropriate action.

Abstract: The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

Abstract: Haptic features are stored in a haptic device by preloading or otherwise downloading them, e.g., wirelessly, into the haptic device at the time of manufacture, immediately prior to game play, during game play, and/or at any other time. Haptic features may be activated, deactivated, modified or replaced at any time. All or a subset of the haptic features may be selected as an active play list, which may be modified as necessary. A host may manage some or all device memory and the haptic features stored therein. Haptic features stored in haptic devices and control information provided by the host are used by the haptic device to execute haptic effects. The haptic device may sustain haptic effects between control messages from the host. New communication messages may be added to an underlying communication protocol to support haptic effects. New messages may use header portions of communication packets as payload portions.

Abstract: A system and method for transferring data flows, such as streaming video or audio signals, between end devices that are members of the same end device group is provided. A network examining module identifies end devices having an active data flow. A data session populating module populates a data store for an end device group identifying end devices having active data flows. A managing module determines which end devices are compatible for a data flow to be transferred. The data flow transferring module transfers the active data flow from one group member end device to another group member end device.

Abstract: A universal plug and play (UPnP)-based network system and a method of controlling the same. A UPnP device can operate according to a description of each control point (CP) when performing a command, by including the description, which is inherent information of each CP, in a command message transmitted from each CP to the UPnP device and allowing the UPnP device to analyze the command message to obtain the description of the CP. The UPnP-based network system includes a plurality of CPs, each of which stores a CP description, which is inherent characteristic information of each CP, and generates and transmits a command message including the CP description, and a UPnP device which is connected to the plurality of CPs over a network, analyzes the command message received from each CP to perform an operation according to the command message, and analyzes the CP description included in the command message to recognize each CP which transmits the command message.

Abstract: A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the receipt of a valid command to the memory device. Upon receipt of a valid command, startup functions are ceased at the high current consumption, and normal operation begins without the need for using an unreliable low voltage power on reset circuit.

Abstract: Multimedia KVM systems are provided. A multimedia KVM system comprises a KVM switch and a local console coupled to the KVM switch. The KVM switch comprises a plurality of first connectors for connecting to a plurality of first multimedia components, respectively. The local console comprises a plurality of second connectors for connecting to a plurality of second multimedia components, respectively. A first user utilizes the first multimedia components, via the local console and the KVM switch, to communicate with a second user utilizing the second multimedia components.

Abstract: An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.

Abstract: Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller device driver and is provided to the host controller as needed to process the queued commands. The host controller is simplified since it only stores the context of the one command being processed. The host controller generates a backoff interrupt when a command cannot be queued. The host controller generates a DMA transfer context request interrupt to request programming of the registers that store the context for the one command being processed.

Abstract: A single fibre channel switch or serial attached SCSI expander applies zoning on the initiator ports to each of the two ports of one or more drives. The fibre channel switch or serial attached SCSI expander uses zoning to connect both ports of each drive to a single expander and set the zones in the expander such that each zone includes at least one initiator port and one drive port.

Abstract: Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays, each of which solves a higher-level sub-problem. The thread arrays are executable by processing cores, each of which can execute at least one thread array at a time. Thread arrays can be grouped into grids of independent thread arrays, which solve still higher-level sub-problems or an entire problem. Thread arrays within a grid, or entire grids, can be distributed across all of the available processing cores as available in a particular system implementation.

Abstract: A system-on-chip including a processor, a control module, a first plurality of data registers, a second plurality of data registers, a plurality of address registers, and a first control module. The first plurality of data registers are configured to store data. The processor is configured to respectively write addresses corresponding to selected ones of the first plurality of data registers in the plurality of address registers. The second plurality of data registers are configured to receive data from the selected ones of the first plurality of data registers. In response to a request from the processor for a first address, the first control module is configured to provide data to the processor from the second plurality of data registers in response to the first address matching an address stored in the plurality of address registers, and otherwise provide data to the processor from the first plurality of data registers.

Abstract: A method of managing a network. The method includes receiving an activation key transmitted from a device connected to the network, automatically transmitting a configuration to the device, automatically maintaining the configuration of the device, and receiving log information from the device.

Abstract: There are provided a transfer request module 2 for interpreting a data transfer request received from outside; a transfer instruction module 1 including a receiving section 10 for receiving the data transfer request after interpretation by the transfer request module 2, a remaining data setting section 12 for setting a data volume to be transferred in accordance with the data transfer request after the interpretation the receiving section 10 receives, a remaining data retaining section 16 for holding the data volume set by the remaining data setting section 12, a remaining data reading section 13 for reading the data volume held in the remaining data retaining section 16, a counter setting section 14 for setting a limit of the number of times of transfer unit settings in accordance with the data transfer request after the interpretation the receiving section 10 receives, a counter 17 for holding the limit of the number of times of the settings carried out by the counter setting section 14 and for counting dow

Abstract: There is provided a direct memory access apparatus and a direct memory access method. The direct memory access apparatus of the present invention comprises: a variable transmission rule map unit for setting a transmission rule with a variable block length and a variable block interval as a unit of memory transmission rule; a direct memory access unit for sending data line of the variable block length and the variable block interval, in case of access to the unit of memory by using the unit of memory transmission rule determined by the variable transmission rule map unit; and an interface unit for retrieving the unit of memory transmission rule, which is necessary for sending the data line of the variable block length and the variable block interval, from the variable transmission rule map unit and sending the unit of memory transmission rule to the direct memory access unit.