Patents Examined by Alfredo Bermudez Lozada
  • Memory controlling device by using multi-phase control signal and method thereof
    Patent number: 10157664
    Abstract: A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is arranged to output an output signal on the pair of bit lines during the first duration.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Atul Katoch, Sergiy Romanovskyy
  • Programming of nonvolatile memory with verify level dependent on memory state and programming loop count
    Patent number: 10157681
    Abstract: A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: December 18, 2018
    Assignee: SanDisk Technologies LLC
    Inventor: Nima Mokhlesi
  • Nonconsecutive sensing of multilevel memory cells
    Patent number: 10153047
    Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Jun Xu
  • Semiconductor device, semiconductor system with the semiconductor device and method of driving the semiconductor system capable of performing refresh operations in units of groups of semiconductor devices
    Patent number: 10147476
    Abstract: A semiconductor device includes a first control block suitable for selectively blocking a refresh command signal based on a period signal having a predetermined activating pattern and a predetermined mode signal activated in a predetermined mode to generate a refresh group signal; and a second control block suitable for controlling a refresh operation based on the refresh group signal.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventor: Choung-Ki Song
  • Clean data strobe signal generating circuit in read interface device
    Patent number: 10147481
    Abstract: A clean data strobe signal generating circuit in a read interface device includes receivers configured to output first and second single ended data strobe signals. In the circuit, a gate signal generating unit is configured to generate a data strobe gate signal synchronized with the first single ended data strobe signal using the first and second single ended data strobe signals and a memory gate signal of which the pulse width varies in accordance with a burst length after termination of a read latency. The gating unit is configured to generate a clean data strobe signal using the first single ended data strobe signal and the data strobe gate signal.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daero Kim
  • Systems and methods for memory cell array initialization
    Patent number: 10127971
    Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Huy T. Vo, Patrick Mullarkey, Jeffrey P. Wright, Michael A. Shore
  • Integrated circuit with overdriven and underdriven pass gates
    Patent number: 10121534
    Abstract: In one embodiment, an integrated circuit includes a pass gate circuit and a memory element circuit. The pass gate circuit receives a user signal that toggles between a high voltage level and a low voltage level. The memory element circuit outputs a control signal to control the pass gate circuit. The control signal may be asserted to be greater than the high voltage level when activating the pass gate circuit or the control signal may be deasserted to be less than the low voltage level when deactivating the pass gate circuit. In addition to that, a method on how to operate the pass gate circuit is also provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 6, 2018
    Assignee: Altera Corporation
    Inventor: Andy L. Lee
  • Magnetic storage device with a wiring having a ferromagnetic layer
    Patent number: 10109331
    Abstract: According to one embodiment, a magnetic storage device includes memory cells, wherein each of the memory cell includes: a wiring including a first ferromagnetic layer and a first nonmagnetic layer disposed on the first ferromagnetic layer; a magnetoresistive effect element including a second ferromagnetic layer disposed on the first nonmagnetic layer, a third ferromagnetic layer, and a second nonmagnetic layer disposed between the second and the third ferromagnetic layer; a first transistor having a first terminal connected to the first ferromagnetic layer, and a second terminal connected to a source line; and a second transistor having a first terminal connected to the third ferromagnetic layer, and a second terminal connected to a bit line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Motoyuki Sato
  • Method and apparatus for stressing a non-volatile memory
    Patent number: 10109356
    Abstract: A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 23, 2018
    Assignee: NXP USA, INC.
    Inventors: Chen He, Richard K. Eguchi, Fuchen Mu, Benjamin A. Schmid, Craig T. Swift, Yanzhuo Wang
  • Multi-bit-per-cell three-dimensional one-time-programmable memory
    Patent number: 10102917
    Abstract: A multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB) comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 16, 2018
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Memory device including memory circuit and selection circuit
    Patent number: 10090023
    Abstract: To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: October 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Ohmaru, Kiyoshi Kato
  • Shaped data associated with an erase operation
    Patent number: 10074427
    Abstract: A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 11, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Idan Alrod, Noam Presman, Ariel Navon, Tz-Yi Liu, Tianhong Yan
  • Scan chain operation in sensing circuitry
    Patent number: 10037785
    Abstract: Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 31, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Debra M. Bell
  • Non-volatile memory with customized control of injection type of disturb during program verify for improved program performance
    Patent number: 10026487
    Abstract: A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for verification, and performing a sensing operation for the memory cell selected for verification in response to the compare signal.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 17, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Programming method for reducing a width of a threshold voltage distribution curve of memory cells
    Patent number: 10026490
    Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 17, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Kuan-Fu Chen
  • Address bit remapping scheme to reduce access granularity of DRAM accesses
    Patent number: 10020036
    Abstract: One embodiment of the present invention sets forth a method for accessing non-contiguous locations within a DRAM memory page by sending a first column address command to a first DRAM device using a first subset of pins and sending a second column address command to a second DRAM device using a second subset of repurposed pins. The technique requires minimal additional pins, space, and power consumption. Further, sending multiple column address commands allows for increased granularity of DRAM accesses and therefore more efficient use of pins. The technique for accessing non-contiguous locations within a DRAM memory page.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 10, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Alok Gupta, Wishwesh Gandhi, Ram Gummadi
  • Semiconductor apparatus capable of improving efficiency for a circuit configuration and a signal line interconnection
    Patent number: 10020030
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 10, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Bong Kim, Geun Il Lee
  • Smart skip verify mode for programming a memory device
    Patent number: 10014063
    Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
  • Memory system and method for reducing read disturb errors
    Patent number: 10014060
    Abstract: A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel E. Tuers, Abhijeet Manohar, Nicholas Thomas, Jonathan Hsu
  • Data path integrity verification in memory devices
    Patent number: 10014070
    Abstract: Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data and the data written to the first register are compared to verify data path integrity.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke