Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming. A method is provided for multiple-page programming of an array having a block that includes page groups and each page group includes cell strings that form pages. The method includes deactivating drain select gates (DSGs) and source select gates (SSG), applying a programming voltage to a selected word line, and applying a middle high voltage to unselected word lines. The method also includes repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation. Each programming operation includes loading data onto bit lines and pulsing a drain select gate associated with a selected page group to load the data into a selected page of the selected page group.

Abstract: A semiconductor device is provided that operates at improved write speeds without an increase in area. The semiconductor device according to the invention includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines provided to each row of the memory cells, a plurality of bit line pairs provided to each column of the memory cells, sense amplifiers that amplify the potential difference in the bit line pairs, data line pairs that transfer data to the bit line pairs, column selection circuits that permit receiving the data from the data line pairs, a column decoder that transmits column selection signals to the column selection circuits, and a sense amplifier control circuit that activates the sense amplifiers after the column decoder transmits the column selection signals to the column selection circuits.

Abstract: A double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) comprises an OTP array stacked on a semiconductor substrate. The OTP array comprises a dummy word line, a plurality of data word lines and data bit lines. The dummy OTP cells at the intersections of the dummy word line and all data bit lines are unprogrammed. During read, both voltages on the dummy word line and a selected data word line are raised.

Abstract: A memory element is provided in which a logical state can be securely stored in all conditions even when input set and reset signals are overlapping. This is achieved through provision of an array of persistence latches with an asynchronous circuit that ensures correct operation. The persistence latches provide a persistent output for each of the first and second edges of each input. The memory element is arranged to receive a plurality of inputs including a first and second input. Each first and second inputs include a digital signal that can transition between a first state via a first edge which triggers transition from the first state to the second state and a second edge which triggers transition from the second state to the first state.

Abstract: PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and controlled by a temperature compensation signal produced at an intermediate node between weak pull-up and strong pull-down PMOS transistors that are connected in series between VDD and VSS and respectively controlled by VDD and VSS during read operations. This configuration generates the temperature compensation signal at a level closer to VSS at high temperatures than at low temperatures, whereby write-ability is not impacted by the read-assist circuit at low temperature.

Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

Abstract: Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

Abstract: A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a first variable resistance element, a first switching element coupled to the first variable resistance element via a first line, a second variable resistance element, and a second switching element coupled to the second variable resistance element via a second line, wherein a distance between the first switching element and the first variable resistance element is larger than a distance between the second switching element and the second variable resistance element, and wherein a second path from a first terminal of the second switching element to the second variable resistance element includes a resistance component, a resistance of the second path being greater than a resistance of a first path, the first path being from a first terminal of the first switching element to the first variable resistance element.

Abstract: A sensing amplification circuit includes a sensing amplifier and a trigger control circuit. The sensing amplifier receives a data voltage and a reference voltage, and outputs a first data signal and a second data signal by comparing the data voltage and the reference voltage. The trigger control circuit includes a logic circuit and a set-reset latch. The logic circuit receives the first data signal and the second data signal, and changes a first control signal from a first voltage level to a second voltage level when one of the first data signal and the second data signal changes its state. The first set-reset latch receives the first control signal and a second control signal, and generates a trigger signal to enable the sensing amplifier when the second control signal changes state and disable the sensing amplifier when the first control signal changes state.

Abstract: Aspects relate to dynamically adapting the number of erase suspend operations on a non-volatile memory (NVM) based on the workload. In some aspects, erase suspend optimization involves computing a workload statistic based on at least read operations performed on the NVM over time, setting a maximum number of erase suspend operations allowed to be performed when the workload statistic compares favorably to a workload threshold, and preventing erase suspend operations from being performed when the workload statistic compares unfavorably to the workload threshold.

Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Abstract: Methods for verifying data path integrity are provided. One such method includes reading a partially programmed first set of data from an array of memory cells of the memory device into a page register of the memory device, loading the partially programmed first set of data into a cache register of the memory device, writing a partial set of test data to a portion of the cache register not containing the partially programmed first set of data during a read of a second set of data from the array of memory cells to the page register, reading the partial set of test data from the cache register during the read of the second set of data from the array of memory cells to the page register, and comparing the partial set of test data read from the cache register to the original partial set of test data.

Abstract: An assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

Abstract: A semiconductor system may be provided. The semiconductor system may include a phase changeable memory device. The phase changeable memory device may include a phase changeable memory cell array, the phase changeable memory cell array may include a plurality of word lines, a plurality of bit lines overlapped with the word lines and phase changeable memory cells respectively connected to overlapping points between the word lines and the bit lines, and the phase changeable memory cell may include a phase changeable material. The semiconductor system may include a controller. The controller may be configured to provide the phase changeable memory device with a command and an address for controlling the phase changeable memory device.

Abstract: A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.