Abstract: A light emitting diode chip and a light emitting diode display apparatus comprising the same, are disclosed in which a screen defect caused by a defect of the light emitting diode chip is minimized. The light emitting diode chip comprises a semiconductor substrate; first and second light emitting diodes provided on the semiconductor substrate in parallel with each other while having first and second pads; a first electrode commonly connected to the first pad of each of the first and second light emitting diodes; and a second electrode commonly connected to the second pad of each of the first and second light emitting diodes, wherein the first and second light emitting diodes are electrically connected to each other in parallel.

Abstract: A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

Abstract: A method for forming a silicon nitride film to cover a stepped portion formed by exposed surfaces of first and second base films in a substrate, includes: forming a nitride film or a seed layer to cover the stepped portion, wherein the nitride film is formed by supplying, to the substrate, a nitrogen-containing base-film nitriding gas for nitriding the base films, exposing the substrate to plasma and nitriding the surface of the stepped portion, and the seed layer is composed of a silicon-containing film formed by supplying a raw material gas of silicon to the substrate and is configured such that the silicon nitride film uniformly grows on the surfaces of the base films; and forming the silicon nitride film on the seed layer by supplying, to the substrate, a second raw material gas of silicon and a silicon-nitriding gas for nitriding silicon.

Abstract: Atomic layer deposition (ALD) processes for forming thin films comprising InN are provided. The thin films may find use, for example, in light-emitting diodes.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a substrate including device regions and isolation regions, adjacent with one another; providing discrete fins on the substrate, pitches between adjacent fins being substantially same; forming a protective layer on the sidewalls of the fins; removing a partial thickness of the fins in the isolation regions along with a partial thickness of the protective layer in the isolation regions by a first etching process; forming dummy fins by a second etching process to etch the remaining fins in the isolation regions using the remaining protective layers as a mask; removing the remaining protective layer after the second etching process; and forming isolation structures in the isolation regions on the substrate. The isolation structures have a top lower than the fins in the device regions and higher than the dummy fins in the isolation regions.

Abstract: The embodiments of the present disclosure provide an array substrate, display panel and display apparatus. The array substrate comprises a plurality of gate lines extending in a row direction; a plurality of data lines extending in a column direction; and an array comprising a plurality of pixels. Each column of pixels of the plurality of pixels are coupled to two data lines of the plurality of data lines, the two data lines are configured to provide same data signal for displaying an image to the column of pixels, a first data line of the two data lines and a second data line of the two data lines are arranged at both sides of the column of pixels along the row direction, respectively. The array substrate, display panel and display apparatus according to the embodiments of the present disclosure can greatly reduce coupling capacitance between a pixel electrode and a data line, thereby an effect of reducing crosstalk can be achieved.

Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.

Abstract: A power semiconductor device package includes a power semiconductor die having a first load terminal at a die frontside and a second load terminal at a die backside. The package has a package top side, a package footprint side, and a first terminal interface and a second terminal interface arranged at the package footprint side. The first terminal interface is electrically connected with the first load terminal. The die is disposed in a main cavity of an insulating core layer. A conductive material is provided at a cavity sidewall of the main cavity, and an insulation structure is provided in the main cavity. The insulation structure embeds the die, with the die backside facing the package top side. An electrical connection provided between the second load terminal and the second terminal interface is formed by at least the conductive material at the cavity sidewall.

Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

Abstract: A multi-layer cooling structure comprising a first substrate layer comprising an array of cooling channels, a second substrate layer comprising a nozzle structure that includes one or more nozzles, an outlet, and an outlet manifold, a third substrate layer comprising an inlet manifold and an inlet, and one or more TSVs disposed through the first substrate layer, second substrate layer, and third substrate layer. At least one of the one or more TSVs is metallized. The first substrate layer and the second substrate layer are directly bonded, and the second substrate layer and the third substrate layer are directly bonded.

Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.

Abstract: The invention relates to an optoelectronic component (100) comprising a semiconductor layer sequence (1) having an active layer (10), wherein the active layer (10) is designed to produce or absorb electromagnetic radiation in intended operation. Furthermore, the component (100) comprises a first contact structure (11) and a second structure (12), by means of which the semiconductor layer sequence (1) can be electrically contacted in intended operation. In operation, a voltage is applied to the contact structures (11, 12), wherein an operation-related voltage difference ?Ubet between the contact structures (11, 12) arises. When the voltage difference is increased, a first arc-over occurs in or on the component (100) between the two contact structures (11, 12). A spark gap (3) between the contact structures (11, 12), which arises in the event of the first arc-over, passes predominantly through a surrounding medium in the form of gas or vacuum and/or through a potting.

Abstract: Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Abstract: Embodiments of the invention form a channel fin across from a major surface of a substrate, wherein a top surface of the channel fin extends substantially horizontally with respect to the major surface. A gate is formed across from the major surface and along a sidewall surface of the channel fin, wherein a first top surface of the gate is above the top surface of the channel fin and extends substantially horizontally with respect to the major surface. A second top surface of the gate is defined by a trench formed through an exposed sidewall portion of the gate in a direction that is substantially horizontal with respect to the major surface, wherein a gate length dimension of the initial gate is defined by a distance from a bottom surface of the gate to the second top surface of the gate.

Abstract: A display apparatus includes a substrate, a first electrode on the substrate, the first electrode including a first portion that has a flat upper surface and a second portion that protrudes from the first portion and has an inclined surface, a second electrode facing the first electrode in parallel on the substrate, the second electrode including a first portion that has a flat upper surface and a second portion that protrudes from the first portion and has an inclined surface, and a plurality of light-emitting devices separate from each other on the first electrode and the second electrode, the light-emitting devices each having a first end contacting the upper surface of the first portion of the first electrode and a second end contacting the upper surface of the first portion of the second electrode.

Abstract: A field-effect transistor includes a source electrode, a drain electrode, a semiconductor structure including a channel provided between the source electrode and the drain electrode in a first direction. Gate main portions have a first gate main portion length in the first direction and a second gate main portion length in a second direction. Connection portions are alternatively connected to the gate main portions respectively in the second direction. Each of the connection portions has a first connection portion length in the first direction and a second connection portion length in the second direction. The first connection portion length is longer than the first gate main portion length. The second connection portion length is shorter than the second gate main portion length. An external connection section is to apply electric power to the gate electrode. A bypass electrode connects the external connection section to each of the connection portions.

Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.