Abstract: A method for manufacturing a semiconductor device is provided. A substrate is provided, where a cover layer is formed on the substrate, a wiring layer is formed in the cover layer, a layer to be etched is formed on the cover layer, and the layer to be etched includes an adhesive layer. An exposure patterned film layer is formed on the layer to be etched. A first etching hole pattern is formed in the exposure patterned film layer. The layer to be etched is etched to form a blind hole by using the exposure patterned film layer as a mask. The exposure patterned film layer is trimmed to form a second etching hole pattern. The layer to be etched is further etched to form a bonding hole by using the trimmed exposure patterned film layer as a mask. A bonding pad is formed in the bonding hole.

Abstract: An integrated circuit device includes a substrate including a first conductivity type region and a second conductivity type region, a first active region arranged in the second conductivity type region, a second active region arranged in the first conductivity type region and spaced apart from the first active region with an isolation region between the second active region and the first active region, an isolation film formed in the isolation region, and a first field cut region extending along the isolation region in a first direction parallel with a channel length direction of each of a first conductivity type transistor on the first active region and a second conductivity type transistor on the second active region.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Abstract: Semiconductor nanoparticles including Ag, In, Ga, and S are provided. In the semiconductor nanoparticles, a ratio of a number of Ga atoms to a total number of In and Ga atoms is 0.95 or less. The semiconductor nanoparticles emit light having an emission peak with a wavelength in a range of from 500 nm to less than 590 nm, and a half bandwidth of 70 nm or less, and have an average particle diameter of 10 nm or less.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: A method for producing a component and a component are disclosed. In an embodiment a method includes providing a substrate, applying a composite of components to the substrate, forming an anchoring layer on the composite of components, attaching a carrier to the anchoring layer, wherein the anchoring layer is disposed between the substrate and the carrier and removing the substrate, wherein the composite of components is divided into a plurality of components by forming a plurality of separating trenches, wherein, after removing the substrate, the components continue to be held on the carrier by the anchoring layer, and wherein the anchoring layer comprises at least one predetermined breaking layer having at least one predetermined breaking position, the predetermined breaking position being laterally surrounded by the separating trenches and—in a plan view of the carrier—being covered by one of the components.

Abstract: Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

Abstract: A method of forming an inverse opal structure along a substrate that includes depositing polymer spheres along the substrate and electroplating the substrate and spheres at a first current density to form a first solid metal layer such that the spheres are raised from the substrate. The method includes electroplating the substrate and the spheres at a second current density to diffuse metals from the substrate and deposit the metal about the spheres. The second current density is greater than the first current density. The method includes electroplating the substrate and spheres to form a second solid metal layer disposed over the spheres, and removing the spheres to form the inverse opal structure disposed between the first and second solid metal layers. The first and second solid metal layers define planar interface surfaces disposed over a porous structure of the inverse opal structure.

Abstract: A conductive pattern for a display device includes a first layer including aluminum or an aluminum alloy disposed on a substrate and forming a first taper angle with the substrate, and a second layer disposed on the first layer forming a second taper angle with the first layer, in which the second taper angle is smaller than the first taper angle.

Abstract: An electronic device includes a first electrode and a second electrode facing each other, an emission layer comprising a plurality of quantum dots, wherein the emission layer is disposed between the first electrode and the second electrode; a first charge auxiliary layer disposed between the first electrode and the emission layer; and an optical functional layer disposed on the second electrode on a side opposite the emission layer, wherein the first electrode includes a reflecting electrode, wherein the second electrode is a light-transmitting electrode, wherein a region between the optical functional layer and the first electrode comprises a microcavity structure, and a refractive index of the optical functional layer is greater than or equal to a refractive index of the second electrode.

Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.

Abstract: Provided is a semiconductor device capable of improving relative accuracy of semiconductor elements and a yield of a semiconductor integrated circuit device. The semiconductor device includes a flat region formed on a surface of a semiconductor substrate, and having an outer peripheral shape formed by regional sides and regional chamfer portions; an outer peripheral region surrounding the flat region, and having a uniform height different from a height of the flat region; a plurality of semiconductor elements having similar shapes or the same shape, and formed on the flat region; and a wiring metal connecting the plurality of semiconductor elements via contact holes formed in a second insulating film on the semiconductor elements.

Abstract: A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad bottom surface, leads laterally spaced apart from the die pad, and a substrate encapsulant interposed between the die pad and the leads and includes a substrate top surface and an opposing substrate bottom surface. The substrate encapsulant is provided such that the die pad and the leads protrude outward from the substrate bottom surface. The method includes providing an electronic device having opposing major surfaces and a pair of opposing outer edges. The method includes connecting the electronic device to the substrate such that one major surface of the electronic device is spaced apart from the die pad top surface and upper surfaces of the leads, and the outer edges overlap an opposing pair of the leads.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: A method of forming an interconnection structure includes following steps. A dielectric structure is deposited over a non-insulator structure. The dielectric structure is etched to form a via opening. A mask layer is formed over the dielectric structure. The mask layer is patterned. An anti-adhesion layer is deposited on a sidewall of the via opening after patterning the mask layer. The dielectric structure is etched to form a trench opening, wherein the patterned mask layer is used as an etch mask during forming the trench opening. A conductive structure is formed in the via opening and the trench opening.

Abstract: A carrier for an optoelectronic component includes a main body, wherein the main body includes a first electrically conductive heating layer arrangement, a first solder layer for soldering an optoelectronic component to the main body is arranged on a first side of the main body, the first electrically conductive heating layer arrangement is electrically insulated from the first solder layer and thermally connected to the first solder layer, and the first heating layer arrangement has an exposed portion on which molten solder of the first solder layer can flow to reduce an electrical resistance of the first heating layer arrangement.

Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.