Abstract: A signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved.

Abstract: The present invention (10) substantially overcomes many of the problems associated with prior art error detection codes by providing a novel approach to detecting and correcting multiple bit errors. The invention (10) organizes the data word into a matrix of n by m bits, where n is the number of m bit groups. Parity bits are generated for each column and each row and used to detect single, double and triple bit errors.

Abstract: The microcomputer of the invention comprises a flip-flop which repeats setting and resetting of a monitor signal. The monitor signal is delivered from an external device in response to a PWM output signal for driving the external device. The flip-flop sets and resets at the front edge, of the monitor signal. The invention detects a failure of the external device according to the presence or absence of inversion of its held value. Hence, the failure of the external device operating at high speeds can be reliably detected by the microcomputer of the invention.

Abstract: A train of signals is generated by clocking an 8-bit word from an 8-bit shift register which has been loaded with an initial data word. The register is provided with feedback loop. The serial data is supplied along a communication link to a similar or identical 8-bit shift register at the receiving end of the link. A comparator compares the output data of the register with the first stage of the register and provides an accept signal provided such comparison indicates inversions at the receipt of each bit for 9-bits onwards. After transmission of 24-bits, the shift register contains the 8-bit data word, which has been checked twice for any inaccuracy.

Abstract: A computer system utilizes a single computer to test the operability of an application which also runs on the same computer. The computer system comprises a processor and a multi-tasking operating system, which is able to execute programs asynchronously and independently of each other in logical environments called sessions. A test case program executes during a first session, and tests an applications program which executes in a second session on the same computer system independently of the test case. The test case program includes commands to input keystrokes to the application under test for processing by the application under test. A test program reads the keystroke and the command from the test case and packetizes the keystroke and command. The test program also runs during the first session. A communication program runs on the processor during a second session and communicates the packetized keystroke and command to the operating system for input to the application under test.

Abstract: This invention relates to a write-back cache which is protected with parity and error correction coding ("ECC"). The parity and ECC codes are generated by a memory interface when data is transferred by main memory to the central processing unit ("CPU") associated with the cache. Thus, all data originating in main memory will be parity and ECC encoded when it passes through the memory interface, and the data, and its related parity information and ECC codes will be stored in the cache. On the other hand, data which is taken from the cache and modified by the CPU during its processing operations is also transferred to the memory interface for ECC encoding. Thus, all data modified by the CPU is also protected, and the modified data, and its related parity information and ECC codes are also stored in the cache.

Abstract: A primary processor provides control, address and data signals to a shadow comparison ASIC which also receives corresponding signals from a shadow processor running in delayed lock step with respect to the primary processor. The primary processor is coupled to a system CPU bus which communicates through a memory interface with a DRAM memory. An EDC circuit generates EDC syndrome bits with respect to data written by the primary processor into the memory through the interface. The EDC syndrome bits are stored in memory along with the data. The shadow comparison ASIC includes an identical EDC circuit for generating comparable syndrome bits from the data transmitted from the primary processor to the memory when in the write mode and from the data transmitted from the memory to the primary processor when in the read mode.

Abstract: A source-level run-time software code debugging instrument (10) includes a target access probe ("TAP") (12) and a communications adapter ("COMDAP") (14) that process emulation commands provided by source-level debugging software operating on a host computer. The TAP includes a TAP CPU (28) that receives target CPU input signals and delivers target CPU output signals for controlling the execution of software code by the target circuit in accordance with command signals provided by the host computer. The TAP also includes a programmable logic cell array (24) and a RAM (34). The TAP logic cell array routes command and data signals to and from the TAP CPU, and the RAM stores an in-circuit emulation ("ICE") program used by the TAP to operate the target circuit. The COMDAP is physically separate from the TAP and provides an interface between the host computer and the TAP. The COMDAP includes a programmable logic cell array (44) and an EPROM (46).

Abstract: A built-in self-test apparatus for a memory cell array having a micro-code sequencer to receive and utilize micro-instruction from a read only memory. The micro-code sequencer applies test algorithms to each cell of the memory cell array and detects the responses to determine the operational status of the memory cell array.

Abstract: A programmable processing device has a built-in a program memory (14) for storage of data including program instructions for controlling a functional unit (20) of the device. The device also includes signature generating means (18) for combining data read from all locations of the memory (14) during a memory test sequence, to generate a signature word which can be used to verify correct programming and operation of the memory. The device includes means for supplying the generated signature word to an instruction decoding means (20) at the end of the memory test sequence for execution as a normal program instruction. The signature word thus directly determines subsequent operation of the device, enabling the verification result to be communicated externally without the need for a dedicated data path for communicating the signature value itself outside the device. Any desired signature word/instruction can be achieved by including a seed word in the stored data.

Abstract: A data reproducing system is provided wherein data stored in an optical disk can be read and, in accordance with a coded error detection and correction code, can have an error pointer defined in synchronization with a modulated data of one symbol. This information can be transmitted, through a time division multiplexing circuit, at a faster clock speed than a demodulating clock with which the timing of a data demodulating will be controlled.

Abstract: An error check or correction code coding device is disclosed. In this device, when a main information code is transmitted after an error check or correction code is added thereto, a control code is included in a code group used in calculations upon generation of the error check or correction code, and a bit pattern of the control code is selected to remove a DC component of the bit pattern of the error check or correction code.

Abstract: A variable length character string detection apparatus comprises a character collating part which registers a character string and compares each character of an input character string with each character making up the registered character string so as to output character string collating signals which respectively indicate whether or not each character of the input character string coincides with one of the characters making up the registered character string, a partial character string detecting part for carrying out predetermined logic operations on the character string collating signals and for outputting partial character string collating signals which respectively indicate whether or not the registered character string which coincides with the input character string and partial character strings thereof exist, and a detection pattern control part for carrying out a predetermined logic operation on the partial character string collating signals and for outputting collating result signals which respectivel

Abstract: A method and apparatus according to the invention detects errors in communicated data words irrespective of the order in which the data words are communicated.

Abstract: A method for performing background disk sector analysis for drives, including drives dedicated to redundancy and/or fault recovery techniques, in an intelligent, microprocessor based disk array. The method directs the microprocessor to wait a specified time and test for disk activity. In the absence of disk activity, the disk controller is directed to generate a read request for a disk memory location within the array. A return code following the array is checked to determine if the read failed, indicating a disk drive media failure. The disk controller is then notified if a failure occurs. The processor again checks for disk array activity and in the absence of activity issues a read request for successive locations within the array, thereby reading all disk memory locations within the array.

Abstract: With employment of an information processing apparatus including a display apparatus, and for executing and debugging a program in an interactive mode, the program is debugged in such a manner that when the program is executed, both a calling relationship between each of modules and an execution history therebetween are sequentially stored, and the dependent relationship between the respective modules (module relation diagram) represented by a tree structure, the execution history of the respective modules, and a source program are displayed. Furthermore, a discriminative display is made to the module which is being executed or in which an error occurs on the module relation diagram, and also a statement source program. In addition, both the module relationship diagram and the module execution history as corresponding with each other an be displayed.

Abstract: A data transmission system and method for processing speech, image and other data disclosed which embodies parallel- and serial-generalized Viterbi decoding algorithms (GVA) that produce a rank ordered list of the L best candidates after a trellis search. Error detection is performed by identifying unreliable sequences through comparison of the likelihood metrics of the two or more most likely sequences. Unreliable sequences are re-estimated using inter-frame redundancy or retransmission.

Abstract: An apparatus for decoding BCH code having first, second and third circuits for generating a syndrome S1, a syndrome S3 and a parity P, respectively from a receiving sequence, a fourth circuit coupled to the first circuit for generating S1.sup.2 from the syndrome S1, a fifth circuit coupled to the first circuit, second circuit and fourth circuit for generating (S1.sup.3 +S3), a Chien search circuit which includes a first generating circuit supplied with the S1 and S1.sub.2 for generating a first stage of error-location polynomial A, where A=S1.alpha..sup.-2n +S1.sup.2 .alpha..sup.-n, and a second generating circuit supplied with the (S1.sup.3 .alpha.+S3) and the A for generating a second stage of error-location polynomial B, wherein B=A+S1.sup.3 +S3, and an error correction and detection logic circuit supplied with the S1, P, (S1.sup.3 +S3), A and B and with a decode selection signal and a BCH code selection signal for generating an error correction or detection signal.

Abstract: A system and method of determining the propagation delay between LSSD (Level Sensitive Scan Delay) latch pairs is performed by modifying system and scan clock sequences. A set bit is initially scanned to the input of the sending trigger. This is done by inhibiting the last B clock. These A and B clocks are then gated off and the system clocks operate a complete cycle with the unique sequence of inhibiting the first latch pulse and the last trigger pulse. Finally, a unique scan clock sequence is used to scan out data from the receiving latch. If the data scanned out corresponds with expected data (the set bit), the process is repeated decreasing the cycle time of the system clocks until the set bit is no longer received. The measured delay is then taken as the preceding cycle time. By measuring the delays between a plurality of points and a common originating point and taking the differences in these delays, the skew in a clock distribution system can be readily determined.

Abstract: A vehicular headlight, in particular an automobile headlight, including a reflector (1) having a reflecting surface, is capable of illuminating a flat target surface to be illuminated with a desired light distribution by optimal utilization of the light source of the headlight. Therefore the optically effective surface of the headlight is characterized by point asymmetry in substantially all planes cutting said reflecting surface. This can be realized by using a method for producing said optical surface comprising the steps of:mathematically representing said surface by creating a spline from bivariate tensor product of polynomials; deriving mathematical data in computer input format from said mathematical representation; and inputting said data to a computer for controlling an apparatus by which the mathematical representation of said optical surface is reproduced in physical form.