Abstract: Disclosed is a DASD access control method including storing information for identifying one data group in which an irrecoverable failure has occurred in the plurality of data groups stored in each of the first and second DASDs constituting the duplex DASD pair. A judgment is determined based on the stored information as to whether one data group has an irrecoverable failure which has occurred when the one data group held in either one of the first and second DASDs constituting the duplex DASD pair is accessed by one of the plurality of processing units. Access is allowed to the one data group in the one DASD by the one processing unit when the judgment results in that the one data group has no irrecoverable failure which has occurred therein. Finally, the access is stopped to the one data group when the judgment results in that the one data group has an irrecoverable failure which has occurred therein.

Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.

Abstract: An optical disk apparatus comprises an optical disk driver for optically recording data to be recorded on an optical disk and optically reproducing recorded data, a RESYNC detecting circuit for detecting a RESYNC code from data reproduced by the optical disk driver, a control circuit for detecting error data occurring due to the erroneous detection of the RESYNC code by the RESYNC detecting circuit and restarting a reproducing operation upon detection of the error data, and a phase inverting circuit for inverting the phase of reproduction data in response to the error detection and outputting phase-inverted reproduction data to the control circuit for an error check. A RESNYC detecting circuit 14 can detect an invalid RESNYC signal by monitoring and comparing binary signal intervals (A1-A5) and reversed signal intervals (B1-B5) as shown in FIG. 3.

Abstract: A data transfer process for transferring data from a first system to a second system while carrying out loop checking, including: a first step for sending out a part of the above data from the first system to the second system; a second step for sending first information that the part of the data has been sent out from the first system to the second system; a third step for receiving the above part of the data in the second system; a fourth step for sending out the part of the data, which has been received in the third step from the second system to the first system; a fifth step for sending second information that the part of the data has been sent out from the second system in the fourth step, a sixth step for receiving the part of the data, which has been sent from the second system, in the first system; a seventh step for determining whether or not the data which has been sent out from the first system in the first step and the data which has been received in the second system in the sixth step are equal;

Abstract: An encoder and decoder for generating and decoding convolutional codes of enhanced orthogonality. In an exemplary embodiment the encoder includes a K bit length shift register for receiving an input serial stream of information bits and providing for each input bit a K bit parallel output to an orthogonal code sequence generator where one of 2.sup.K-1 symbol sequences is generated with each symbol sequence of a K-2 symbol length. The encoded symbol stream is decoded using an orthogonal function generator driven by a K-2 binary counter to generate all possible symbol sequences for comparison with each received symbol sequence. The output of the comparison is Viterbi decoded to provide the original stream of information bits. Corresponding methods of encoding the information bits and decoding of the symbol sequences are included.

Abstract: A dual data check apparatus is included in a system which includes at least one pair of electronic disk units which store identical data and an electronic disk controller connected to the two electronic disk units through an interface which can realize daisy-chain connections. One of the pair of electronic disk units includes an output unit for supplying to the interface data corresponding to a read command sent from the electronic disk controller. The other of the pair of electronic disk units includes a unit for fetching the data supplied from the output unit to the interface, comparing the fetched data with data read out in the other electronic disk unit in response to the read command, and signaling an error event to the electronic disk controller when a comparison result represents a noncoincidence.

Abstract: A plurality of gates are arranged between a coincidence circuit and a group of comparators which compare data outputted by a processor's output buffers, and data inputted to the processor via terminals during a monitor mode. An invalid byte information generator is connected to the gates and applies a signal selected to mask the effects of write instructions being executed on an incomplete word and therefore prevents the generation of an erroneous mismatch signal.

Abstract: Herein disclosed according to the present invention are method and apparatus of two-degrees-of-freedom time difference comparison compensator. In a control system using a conventional regulator, a desired value or reference value is inputted to the regulator through a versatile time difference compensator. The apparatus may be constructed in the form of a versatile control apparatus to be realized as a hardware, a software or a composite having the two functions, an exclusive control apparatus, or a built-in control apparatus for an individual control system. Thus, the control system to be provided has an excellent effects in the relevant industry because it can make adjustments to the highest state while satisfying several characteristics such as the quickness of response and the stabilizability of perturbations or other several characteristics such as robust stabilizability simultaneously.

Abstract: A stereolithography system employing a more powerful laser and faster dynamic mirrors to speed up part building without sacrificing accuracy is described, especially large or complex parts. A controllable shutter is placed in the beam path of the laser to selectably block the passage of the beam and prevent unwanted solidification. A suitable servo controlled feedback loop is provided to accurately position the mirrors at the higher velocity.Also described is a means to reduce data flow by distributing tasks in a multiple processor environment, and to improve user interaction by the use of a spreadsheet model. These also improve the speed of part building, especially for large or complex parts.

Abstract: A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.

Abstract: An error correction circuit is provided which uses NMOS and PMOS synapses to form neural network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.

Abstract: Code data of input type and output type low-speed interface units installed in one and other optical data transmission apparatus, placed opposite to and operatively connected to each other, are compared automatically in the one and the other optical data transmission apparatus respectively with code data of input type and output interface units in the other optical data transmission apparatus, sent from the other to the one optical data transmission apparatus and with code data of input type and output interface units in the one optical data transmission apparatus, sent from the one to the other optical data transmission apparatus.

Abstract: The present invention method is of the type which may be implemented in existing maintenance controllers of large mainframe computers and comprises a method for checking hardware errors which exists in the computing system and are displayable on a display of the type employed to display the state of scan settable latches. The novel method permits a more compact display of the functional operation of the computing system thus permitting a customer engineer to easily identify a faulty latch copy based solely on employing the method and prescribed format. The novel method includes assimilating the state of scannable logic devices such as latches and designators in the computer system and defining functionally the system in which they are located. The binary state of the individual latches are then subdivided into a plurality of one or more groups having the same number of copies and are assigned to a duplicate pseudo having four unique features which define each of the latches in a group.

Abstract: An apparatus and method for accurately and rapidly machining a workpiece, particularly for drilling holes smaller than can be formed by other methods, by using a high power pulsed Nd:YAG laser. A low power HeNe laser is joined to the optical path of the high power laser. The colinear beams then scan along one axis of the workpiece. The low power beam is partially split off to a location determining device before final deflection to the workpiece. Deflection in a second axis is achieved by linearly moving the workpiece so that the beam will impinge upon the desired location of the workpiece.

Abstract: A mass storage apparatus, made up of a plurality of physical storage devices, which is capable of providing both high bandwidth and high operation rate, as necessary, along with high reliability, is provided. The device set is divided into one or more redundancy groups. Each redundancy group is in turn divided into one or more data groups, each of which may span only a small number of the drives in the redundancy group, providing a high request rate, or which may span a large number of drives, providing high bandwidth.

Abstract: A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell.

Abstract: An auxiliary monolithic integrated circuit chip provides both buffer amplification and testing interfaces. Off-the-shelf monolithic integrated circuit chips can be connected into an electronics system using one of these auxiliary buffer chips before each input port and after each output port, to implement functional testing similar to that done on monolithic integrated circuit chips with built-in test circuitry.

Abstract: The control system is programmable by the user by inserting a preprogrammed key into the system console. The key changes the default values normally used by the control system to those values selected by a particular surgeon. The control console thus emulates the performance characteristics of a wide variety of different types of microsurgical control systems, leaving the surgeon free to perform the operation without having to adjust to a new or unfamiliar system. The display screen is self-illuminating and provides a plurality of control menus generated by data stored in computer memory circuits. By bank switching the memory circuits, the display can be caused to appear in a wide variety of different languages.

Abstract: A control method for the rotational frequency of a weaving machine comprises the steps of performing a plurality of times of trial runnings of the weaving machine at different trial rotational frequencies to obtain the operating time for each rotational frequency, obtaining at least one indefinite coefficient in the formula representing the relation between a rotational frequency factor and an operating time factor by utilizing each obtained operating time and each trial rotational frequency, obtaining the optimum rotational frequency, at which the quantity of production reaches the maximum, on the basis of the obtained at least one indefinite coefficient and fuzzy inference, and controlling the rotational frequency of the weaving machine into the obtained optimum rotational frequency.

Abstract: A semiconductor memory device having a self-correcting function comprises memory cells for storing data and memory cells for storing parity bit data. The criterion of detecting in the first read circuit is set smaller and the criterion of detecting in the second read circuit is set greater in value than the current value read in such a state that the electric charge in the memory cell becomes depleted. In this way, the first read circuit detects a current value smaller and the second read circuit detects a current value greater than the value of the current flowing through the memory cell holding the bit error because of charge depletion. Consequently, even if the variation of the threshold resulting from the charge depletion allows the presence of a faulty memory cell, one of the read circuits can make a correct data read.