Patents Examined by Allen Parker
  • Patent number: 10312225
    Abstract: A display apparatus and a micro-light emitting diode are disclosed. The display apparatus includes: a first substrate including a light emitting diode part including a plurality of light emitting diodes regularly arranged on the first substrate. The display apparatus is implemented using micro-light emitting diodes formed of nitride semiconductors and thus can provide high efficiency and high resolution to be applicable to a wearable apparatus while reducing power consumption. The micro-light emitting diodes may include a wall element so as to be applied to a display substrate by force.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 4, 2019
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Young Hyun Kim
  • Patent number: 10224418
    Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengwen Pei, Xusheng Wu, Ziyan Xu
  • Patent number: 10199239
    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 10192995
    Abstract: A semiconductor device includes a semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first conductor and the semiconductor partly overlap with each other with the first insulator positioned therebetween. The second conductor and the third conductor have regions in contact with the semiconductor. The semiconductor has a region in contact with the second insulator. The fourth insulator has a first region and a second region. The first region is thicker than the second region. The first region has a region in contact with the second insulator. The second region has a region in contact with the third insulator. The fourth conductor and the second insulator partly overlap with each other with the fourth insulator positioned therebetween.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: January 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Patent number: 10186525
    Abstract: The present invention provides a circuit board having excellent productivity, particularly a circuit board having excellent productivity with respect to a semiconductor layer and source layer forming step, a display device, and a process for producing a circuit board. The circuit board of the present invention is a circuit board including an oxide semiconductor layer and an electrode connected to the oxide semiconductor layer, wherein the electrode is formed by essentially laminating a layer made of a metal other than copper and a layer containing copper.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 22, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuichi Saito, Yohsuke Kanzaki, Yudai Takanishi, Tetsuya Okamoto, Yoshiki Nakatani, Yoshimasa Chikama
  • Patent number: 10186477
    Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 22, 2019
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 10186832
    Abstract: A method for fabricating a surface emitting laser includes the steps of: preparing a processing apparatus with a first part and a second part, the processing apparatus including a first heater and a second heater that heat the first part and the second part, respectively; preparing a wafer product for forming a surface emitting laser, the wafer product including a semiconductor post including a III-V compound semiconductor layer containing aluminum as a constituent element, the III-V compound semiconductor layer being exposed at a side face of the semiconductor post; after disposing the wafer product in the second part, energizing the first heater and the second heater; supplying a first gas containing no oxidizing agent to the processing apparatus; and after stopping supplying the first gas, oxidizing the III-V compound semiconductor layer by supplying a second gas containing an oxidizing agent to the processing apparatus.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yukihiro Tsuji
  • Patent number: 10153307
    Abstract: A semiconductor device is provided in which ESD is less likely to occur in a manufacturing process thereof. In manufacture of a semiconductor device including a long lead wiring A, during steps with direct exposure to a plasma atmosphere, a plurality of island-shaped wirings is formed for the wiring A and then electrically connected to one another in series. Specifically, a plurality of island-shaped wirings is formed, covered with an insulating layer, and electrically connected to one another in series by a wiring formed over the insulating layer. The island-shaped wiring and the wiring formed over the insulating layer are electrically connected to each other through an opening formed in the insulating layer.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10153384
    Abstract: A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 11, 2018
    Assignee: SunPower Corporation
    Inventor: Thomas Pass
  • Patent number: 10134664
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: November 20, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Patent number: 10128322
    Abstract: An organic light-emitting display device includes: a substrate; a thin film transistor over the substrate, the thin film transistor including a semiconductor layer and a gate electrode overlapping the semiconductor layer; a conductive layer between the substrate and the semiconductor layer of the thin film transistor; an insulating layer between the conductive layer and the thin film transistor; a passivation layer covering the thin film transistor; a pixel electrode over the passivation layer, the pixel electrode being electrically connected to the thin film transistor via a contact hole defined in the passivation layer; an emission layer over the pixel electrode; and an opposite electrode over the emission layer, the opposite electrode being electrically connected to the conductive layer.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Soonmyung Hong, Kyongtae Park
  • Patent number: 10121656
    Abstract: Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Wei Jiang, Zhiwei Lin, Xiangjing Zhuo, Tianzu Fang, Yang Wang, Jichu Tong
  • Patent number: 10109754
    Abstract: Disclosed is at least one embodiment of an infrared (IR) photovoltaic (PV) detector, comprising a IV-VI Lead (Pb)-salt layer disposed on a substrate and a charge-separation-junction (CSJ) structure associated with the IV-VI Pb-salt layer, wherein the CSJ structure comprises a plurality of element areas disposed upon or within the IV-VI Pb-salt layer, wherein the plurality of element areas are spaced apart from each other. Each element area may be connected to a first Ohmic contact thereby forming a plurality of interconnected first Ohmic contacts, and a second Ohmic contact may be disposed upon a portion of the IV-VI Pb-salt layer. In another non-limiting embodiment, a PV detector, comprising a heterojunction region that comprises at least one IV-VI Pb-salt material layer coupled to at least one non-Pb-salt layer, wherein the at least one IV-VI Pb-salt layer and the at least one non-Pb-salt layer form a p-n junction or Schottky junction with a type II band gap alignment.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 23, 2018
    Assignee: The Board of Regents of the University of Oklahoma
    Inventor: Zhisheng Shi
  • Patent number: 10084079
    Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Yoo, Kwan-Young Kim, Jin-Hyun Noh, Kee-Moon Chun, Yong-Woo Jeon
  • Patent number: 10062741
    Abstract: A method of manufacturing joined body including: firstly, putting sheet material in intimate contact with first substrate to cover, with resin layer of sheet material, areas of first substrate including first area, boundary area surrounding first area, and second area located across from first area with respect to boundary area, sheet material being laminate including resin layer and separable layer, resin layer containing uncured sealing resin; secondly, curing sealing resin in part of resin layer covering boundary area; thirdly, removing, along with separable layer, part of resin layer covering second area in one direction from one end towards the other of two ends of second area; and fourthly, joining first substrate and second substrate together by arranging second substrate to face first substrate and curing sealing resin with parts of resin layer covering boundary area and first area located between second substrate and first substrate.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: August 28, 2018
    Assignee: JOLED INC.
    Inventors: Hiroko Okumura, Takuya Satoh
  • Patent number: 10062642
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 28, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Igarashi, Takuo Funaya
  • Patent number: 10050086
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 14, 2018
    Assignee: Unity Semiconductor Corporation
    Inventors: Lidia Vereen, Bruce L. Bateman, David A. Eggleston, Louis C. Parrillo
  • Patent number: 10008958
    Abstract: The present invention relates to a method of manufacturing a capacitive micro-machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), and depositing a second electrode layer (50) on the second dielectric film (40), wherein the first dielectric film (20) and/or the second dielectric film (40) comprises a first layer comprising an oxide, a second layer comprising a high-k material, and a third layer comprising an oxide, and wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: June 26, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Peter Dirksen, Ruediger Mauczok, Koray Karakaya, Johan Hendrik Klootwijk, Bout Marcelis, Marcel Mulder
  • Patent number: 9997686
    Abstract: A low-cost conductive carrier element provides structural support to a light emitting device (LED) die, as well as electrical and thermal coupling to the LED die. A lead-frame is provided that includes at least one carrier element, the carrier element being partitioned to form distinguishable conductive regions to which the LED die is attached. When the carrier element is separated from the frame, the conductive regions are electrically isolated from each other. A dielectric may be placed between the conductive regions of the carrier element.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: June 12, 2018
    Assignee: LUMILEDS LLC
    Inventors: Qingwei Mo, Dirk Paul Joseph Vanderhaeghen
  • Patent number: 9997739
    Abstract: Disclosed white organic light emitting device includes an anode and a cathode opposing each other; a charge generation layer interposed between the anode and the cathode; a first stack interposed between the anode and the charge generation layer, the first stack including a first hole transport layer and a first light emitting layer emitting blue fluorescent light; and a second stack interposed between the charge generation layer and the cathode, the second stack including a second hole transport layer and a second light emitting layer formed by doping one host with at least one of phosphorescent dopant, wherein a triplet energy level of the first hole transport layer is higher than a triplet energy level of the first light emitting layer, and a hole mobility of the first hole transport layer is 5.0×10?4 cm2/s·V to 9.9×10?3 cm2/s·V.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: June 12, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Ki-Woog Song, Sung-Hoon Pieh, Sung-Jae Ko