Abstract: A semiconductor device includes a gate electrode having higher Gibbs free energy for oxidation than a gate insulating film. An oxide semiconductor layer having a fin shape is formed over an insulating surface, a gate insulating film is formed over the oxide semiconductor layer, a gate electrode including an oxide layer and facing top and side surfaces of the oxide semiconductor layer with the gate insulating film located therebetween is formed, and then by performing heat treatment, a gate electrode is reduced and oxygen is supplied to the oxide semiconductor layer through the gate insulating film.

Abstract: An LED leadframe or LED substrate includes a main body portion having a mounting surface for mounting an LED element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the LED element is disposed over the mounting surface of the main body portion. The reflection metal layer comprises an alloy of platinum and silver or an alloy of gold and silver. The reflection metal layer efficiently reflects light emitted from the LED element and suppresses corrosion due to the presence of a gas, thereby capable of maintaining reflection characteristics of light from the LED element.

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

Abstract: A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Abstract: A light-emitting device includes: a photoluminescent layer that emits light; and a light-transmissive layer on which the emitted light is to be incident. At least one of the photoluminescent layer and the light-transmissive layer defines a surface structure. The surface structure has projections and/or recesses to limit a directional angle of the emitted light. The photoluminescent layer and the light-transmissive layer are curved.

Abstract: Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad.

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51).

Abstract: Provided are an epitaxial wafer and a method of fabricating the same. The method includes a pre-growth step of injecting a reaction source for epitaxial growth on a semiconductor wafer prepared in a chamber and growing an epitaxial layer by a predetermined first thickness at a predetermined first growth rate and at a predetermined first growth temperature, a heat treatment step of performing heat treatment on the epitaxial layer grown by the pre-growth step during a predetermined time, and a subsequent growth step of injecting the reaction source on the heat-treated semiconductor wafer and growing the epitaxial layer to a target thickness at a predetermined second growth rate and at a predetermined second growth temperature. The first growth rate is smaller than the second growth rate.

Abstract: A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.

Abstract: A random access point is generated in a stream of coded digital pictures containing a plurality of predictive coded frames that have two or more predictive coded frames in which one or more subsections of each of the two or more predictive coded frames are intra coded. Information is added to a stream of digital pictures that identifies for a decoder which of two or more predictive-coded frames in the stream have intra-coded subsections at different portions that can be combined to form a patch frame.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a memory cell structure formed over the substrate. In addition, the memory cell structure includes a first electrode layer formed over the substrate and a resistance-change material layer formed over the first electrode layer. The memory cell structure further includes a second electrode layer formed over the resistance-change material layer. In addition, the resistance-change material layer includes a semimetal or a semimetal alloy.

Abstract: Oxygen is likely to be released or an oxygen vacancy is likely to occur during a manufacturing process particularly at a side surface of an oxide semiconductor layer. When an oxygen vacancy occurs at the side surface of the oxide semiconductor layer, a problem arises in that the resistance of the side surface is reduced, the apparent threshold voltage of a transistor varies, and variation in the threshold voltage is increased. Further, the variation in the threshold voltage may cause unintentional current to flow between a source and a drain, which might lead to an increase in the off-state current of the transistor and deterioration in the electric characteristics of the transistor. A semiconductor device in which a multilayer film including an oxide semiconductor layer and an oxide layer surrounding the oxide semiconductor layer is used for a channel formation region is provided.

Abstract: A package structure with an optical barrier is provided. An emitter for emitting an optical signal and a detector for receiving the optical signal are disposed on a substrate. The optical barrier is disposed between the emitter and the detector for shielding the excess optical signal. A package material is used to completely cover the optical barrier, the emitter and the detector so that the optical barrier is completely disposed within the package material.

Abstract: The present disclosure relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a substrate, a first transistor and a first patterned conductive layer. The first transistor has a source region, a drain region in the substrate and a gate region on the substrate. The first patterned conductive layer is electrically connected to the drain region of the first transistor. The first patterned conductive layer includes a first section, a second section and a fusible device.

Abstract: A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a source/drain region on the substrate. A first insulator layer is formed on the source/drain region. A portion of the first insulator layer is removed to expose portions of the spacers. Exposed sidewall portions of the spacers are removed to reduce a thickness of the exposed portions of the spacers. A protective layer is deposited over the exposed sidewalls of the spacers and a second insulator layer is deposited over the protective layer. The sacrificial gate is removed to expose a channel region of the substrate. A gate stack is formed over the channel region of the substrate. Exposed portions of the first insulator layer and the second insulator layer are removed to expose the source/drain region, and a conductive is formed on the source/drain region.

Abstract: Disclosed herein are semiconductor devices and methods for fabricating a semiconductor device. In an embodiment, a method of fabricating a semiconductor device comprises providing a substrate. The method further comprises forming, on the substrate, an array region having a first height, a peripheral region having a second height greater than the first height, and a border region, the border region separating the array region from the peripheral region. The method further comprises forming a plurality of alternating insulative and conductive layers over at least a portion of the array region and the border region. The method further comprises forming a trench through the plurality of alternating insulative and conductive layers in at least a portion of the border region, the trench having sloping sidewalls.

Abstract: A light emitting device includes a first substrate, a second substrate and a plurality of micro epitaxial structures. The second substrate is disposed opposite to the first substrate. The micro epitaxial structures are periodically disposed on the substrate and located between the first substrate and the second substrate. A coefficient of thermal expansion of the first substrate is CTE1, a coefficient of thermal expansion of the second substrate is CTE2, a side length of each of the micro epitaxial structures is W, W is in the range between 1 micrometer and 100 micrometers, and a pitch of any two adjacent micro epitaxial structures is P, wherein W/P=0.1 to 0.95, and CTE2/CTE1=0.8 to 1.2.

Abstract: Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.

Abstract: A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings.