Patents Examined by André C. Stevenson
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Patent number: 7018888Abstract: The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).Type: GrantFiled: July 30, 2004Date of Patent: March 28, 2006Assignee: Texas Instruments IncorporatedInventors: Brian E. Goodlin, Amitava Chatterjee, Shirin Siddiqui, Jong S. Yoon
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Patent number: 6909111Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.Type: GrantFiled: December 19, 2001Date of Patent: June 21, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hirokazu Yamagata, Yoshimi Adachi, Noriko Shibata
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Patent number: 6861268Abstract: The present invention provides a method for inspecting a silicon wafer making it possible to identify and efficiently detect a new defect affecting a device fabricating process, a method for manufacturing a silicon wafer enabling manufacture of wafers not having the defect, a method for fabricating a semiconductor device using the silicon wafer not having this defect, and the silicon wafer not having the defect. When a silicon wafer is inspected, inspection is made for a defect having the entire defect size of 0.5 ?m or more in which microdefects gather in a colony state.Type: GrantFiled: August 21, 2001Date of Patent: March 1, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Miho Iwabuchi
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Patent number: 6859262Abstract: A system delivers radiation to a substrate with a radiation source to generate radiation having a source intensity distribution pattern; and a redistribution radiation guide adapted to receive the radiation from the radiation source and to direct the radiation from one region to different regions on the substrate so that the substrate intensity distribution pattern is different from the source pattern.Type: GrantFiled: December 6, 2000Date of Patent: February 22, 2005Assignee: Tegal CorporationInventor: Tue Nguyen
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Patent number: 6791679Abstract: A correlation between develop inspect (DI) and final inspect (FI) profile parameters are established empirically with test wafers. During production, a wafer is measured at DI phase to obtain DI profile parameters and FI phase profile parameters are predicted according to the DI profile parameters and the established correlation. Each wafer is subsequently measured at FI phase to obtain actual FI profile parameters and the correlation is updated with actual DI and FI profile parameters.Type: GrantFiled: February 4, 2003Date of Patent: September 14, 2004Assignee: Timbre Technologies, Inc.Inventors: Daniel Edward Engelhard, Manuel B. Madriaga
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Patent number: 6734924Abstract: Disclination of an active matrix liquid crystal display device is reduced. Portions of pixel electrodes are formed so as to mutually overlap with a convex portion. If the height of the convex portion is too tall, the amount of light leakage increases due to liquid crystals orienting diagonally with respect to a substrate surface. (See FIG. 1C.) If the height of the convex portion is low, the disclination reduction effect is low. The optimal convex portion height is thus determined.Type: GrantFiled: September 7, 2001Date of Patent: May 11, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiharu Hirakata, Yuriko Hamamoto, Rumo Satake
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Patent number: 6528331Abstract: The invention is, in its various aspects, a method and apparatus for processing a semiconductor wafer. More particularly, the invention is a method and apparatus for identifying and controlling the impact of ambient conditions on photolithography processes. In a first aspect, the invention is a method for processing a semiconductor wafer. The method comprises identifying a disturbance in a photolithographic process arising from an ambient condition; modeling the identified disturbance; and applying the model to modify a control input parameter. In a second aspect, the invention is an apparatus for controlling a photolithography process. The apparatus includes an exposure tool, including a photolithography controller; and a computer receiving data from the exposure tool.Type: GrantFiled: March 8, 2002Date of Patent: March 4, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Christopher A. Bode, Anthony J. Toprac
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Patent number: 6524871Abstract: A defect inspection apparatus enabling more reliable and quicker detection of a defect present in the surface of a stacked film formed on a wafer and enabling reliable and quicker detection of a minute defect even if there is unevenness in the surface of the wafer, including a light source, a light frequency shifter unit for converting light from the light source to a plurality of beams of inspection light and a beam of reference light having close frequencies, an object lens upon which the beams of inspection light are incident and focusing the beams of light on the wafer to form a plurality of different focal points corresponding to the beams of inspection light, a laser scanning unit for making the beams of inspection light scan the wafer, a light detection unit and cofocal pinhole plate 13 for detecting an intensity of a superposed light of the beams of reflected light and the beam of reference light at a cofocal point, and an analyzing unit serving as a contrast waveform generating means for generating aType: GrantFiled: January 8, 2002Date of Patent: February 25, 2003Assignee: Sony CorporationInventor: Kouki Okawauchi
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Patent number: 6524873Abstract: Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.Type: GrantFiled: August 25, 2000Date of Patent: February 25, 2003Assignee: KLA-TencorInventors: Akella V. S. Satya, David L. Adler, Bin-Ming Benjamin Tsai, Neil Richardson, David J. Walker
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Patent number: 6514345Abstract: A semiconductor manufacturing apparatus is improved so that apparatus operating condition parameters can be restored to setting values of various levels such as standard, apparatus delivery time or client oriented setting values even if the parameters are overwritten. The semiconductor manufacturing apparatus is constituted by a multi-chamber processing system 4, a transport system 8 of an object and an equipment control unit 210 having a memory apparatus 214 storing the apparatus operating condition parameters and providing the parameters to machine control units 150, 72. The machine control units 150, 72 controls the processing system 4 and the transport system 8 based on the apparatus operating condition parameters.Type: GrantFiled: September 21, 2000Date of Patent: February 4, 2003Assignee: Tokyo Electron LimitedInventors: Masaya Nagata, Masahiro Sugawara
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Patent number: 6514781Abstract: A method and apparatus for maintaining the state of a MEMS device in the event of a power failure are disclosed. The apparatus and method may be used with a MEMS device generally having one or more MEMS elements moveably coupled to a substrate that uses electrostatic clamping force to sustain the state of the MEMS element. According to the method, a capacitive or other charge-storing circuit is coupled between a clamping surface and an electrical ground. During normal operation, a clamping voltage is applied between the clamping surface and at least one MEMS element to retain the at least one MEMS element against the clamping surface. In the event of a power failure, the source of the clamping voltage and other circuit paths to ground are isolated from the clamping surface. The charge-storing circuit maintains an electric charge on the clamping surface.Type: GrantFiled: July 7, 2001Date of Patent: February 4, 2003Assignee: Onix Microsystems, Inc.Inventors: Mark W. Chang, Scott D. Dalton, Michael J. Daneman, Timothy Beerling, Stephen F. Panyko, Gary M. Zalewski
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Patent number: 6486492Abstract: A method and apparatus for reducing lot to lot CD variation in semiconductor wafer processing feeds back information gathered during inspection of a wafer, such as after photoresist application, exposure and development, to upcoming lots that will be going through the photolithography process, and feeds forward information to adjust the next process the inspected wafer will undergo (e.g., the etch process). Embodiments include forming a feature such as an etch mask on a semiconductor wafer at a “photo cell” by a photolithography process, then conventionally imaging the feature with a CD-SEM to measure its CD and other sensitive parameters. The measured parameters are linked, via the feature's SEM waveform, to photolithography adjustable parameters such as stepper focus and exposure settings.Type: GrantFiled: November 20, 2000Date of Patent: November 26, 2002Assignee: Applied Materials, Inc.Inventor: Bo Su
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Patent number: 6487711Abstract: A method of analyzing factor responsible errors in a wafer pattern which enables detection of an error ascribable to a difference between mask patterns and an error ascribable to another reason while distinguishing between the errors. A mask pattern is formed by etching a first mask at a first position within an etching chamber. Another mask pattern is formed by etching a second mask at a second position within the etching chamber. A wafer pattern is formed by single shot of exposing radiation through use of the first mask, and another wafer pattern is formed by single shot of exposing radiation through use of the second mask. The size of the wafer pattern formed through use of the first mask and the size of the wafer pattern formed through use of the second mask are compared with each other, thereby detecting a dimensional difference ascribable to a difference between mask patterns and a dimensional difference ascribable to another reason while distinguishing between the dimensional differences.Type: GrantFiled: May 22, 2000Date of Patent: November 26, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tsutomu Koike
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Patent number: 6274395Abstract: A method of fabricating a semiconductor wafer includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. In addition, the method includes the step of storing the test data obtained during the testing step in the memory device. Moreover, the method includes the step of retrieving the test data from the memory device. Yet further, the method includes the step of operating a packaging apparatus so as to package a first die of the number of die based on the test data. A semiconductor wafer is also disclosed.Type: GrantFiled: December 23, 1999Date of Patent: August 14, 2001Assignee: LSI Logic CorporationInventor: David M. Weber