Patents Examined by André C. Stevenson
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Patent number: 11610982Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.Type: GrantFiled: January 4, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
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Patent number: 11610914Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.Type: GrantFiled: January 28, 2021Date of Patent: March 21, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Tianhong Yan, Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari
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Patent number: 11610981Abstract: A method for manufacturing a semiconductor device comprising: providing a substrate, wherein an amorphous silicon layer is formed on the substrate; forming an etching auxiliary layer on the amorphous silicon layer, wherein the upper surface of the etching auxiliary layer is flat, and the etching auxiliary layer is made of a single material; and etching the amorphous silicon layer and the etching auxiliary layer to obtain an amorphous silicon layer with a target thickness, wherein the upper surface of the etched amorphous silicon layer is flat.Type: GrantFiled: April 7, 2021Date of Patent: March 21, 2023Assignee: Shanghai Huali Integrated Circuit CorporationInventors: Changhung Kung, Xiantao Li, Xiumei Hu, Jianxun Chen, Chanyuan Hu
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Patent number: 11610973Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.Type: GrantFiled: December 28, 2021Date of Patent: March 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
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Patent number: 11600717Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.Type: GrantFiled: October 13, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shih-Yao Lin, Pei-Hsiu Wu, Chih Ping Wang, Chih-Han Lin, Jr-Jung Lin, Yun Ting Chou, Chen-Yu Wu
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Patent number: 11594423Abstract: The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.Type: GrantFiled: January 17, 2022Date of Patent: February 28, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Qiang Wan
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Patent number: 11574846Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.Type: GrantFiled: October 20, 2020Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Jhih Syu, Chih-Hao Yu, Chang-Yun Chang, Hsiu-Hao Tsao, Yu-Jiun Peng
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Patent number: 11562928Abstract: A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern formed using laser marking on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the at least one code pattern is visible from a backside of the chip, the at least one code pattern represents a binary number having four bits; and the binary number represents a decimal number to represent a tracing number of the chip.Type: GrantFiled: January 25, 2019Date of Patent: January 24, 2023Assignee: OmniVision Technologies, Inc.Inventors: Wei-Feng Lin, Chi-Chih Huang
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Patent number: 11551924Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.Type: GrantFiled: July 22, 2020Date of Patent: January 10, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Shiliang Ji, Bo Su, Haiyang Zhang
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Patent number: 11548804Abstract: There is provided a method of processing an oxygen-containing workpiece. The method of processing an oxygen-containing workpiece includes controlling a fluorine concentration in the oxygen-containing workpiece based on at least one of a kind of a fluorine-containing processing gas, a processing temperature and a processing pressure used for processing the oxygen-containing workpiece.Type: GrantFiled: August 1, 2019Date of Patent: January 10, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Reiko Sasahara, Yasuo Nakatani, Keiko Hada
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Patent number: 11536999Abstract: A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.Type: GrantFiled: March 1, 2021Date of Patent: December 27, 2022Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Hideo Tanabe, Masaru Takabatake, Toshiki Kaneko, Atsushi Hasegawa, Hiroko Sehata
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Patent number: 11538818Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.Type: GrantFiled: July 21, 2021Date of Patent: December 27, 2022Assignee: Winbond Electronics Corp.Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao
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Patent number: 11515400Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.Type: GrantFiled: September 1, 2020Date of Patent: November 29, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Ruizhi Tang, Jinyu Fu, Lin Liu, Bo Li, Peng Yang, Haojun Huang, Jialei Liu
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Patent number: 11508628Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.Type: GrantFiled: September 15, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
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Patent number: 11508572Abstract: A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.Type: GrantFiled: April 1, 2020Date of Patent: November 22, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chun-Yi Chou, Po-Hsien Cheng, Tse-An Chen, Miin-Jang Chen
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Patent number: 11502041Abstract: The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.Type: GrantFiled: April 22, 2020Date of Patent: November 15, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ying-Cheng Chuang
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Patent number: 11495681Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.Type: GrantFiled: October 12, 2020Date of Patent: November 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Po Hsiung, Ching-Chung Yang, Shan-Shi Huang, Shin-Hung Li, Nien-Chung Li, Wen-Fang Lee, Chiu-Te Lee, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
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Patent number: 11488870Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.Type: GrantFiled: April 8, 2020Date of Patent: November 1, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tien-Yu Hsieh, Kuan-Ti Wang, Han-Chen Chen, Kun-Hsien Lee
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Patent number: 11482426Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.Type: GrantFiled: January 20, 2021Date of Patent: October 25, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ying Lee, Jyu-Horng Shieh
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Patent number: 11476113Abstract: There is provided a technique having a process that includes forming a film, which contains a first element and a second element on a substrate by performing a cycle a predetermined number of times, the cycle sequentially performing: (a) supplying a first precursor gas containing the first element to the substrate in a process chamber; (b) supplying a second precursor gas, which contains the first element and has a pyrolysis temperature lower than a pyrolysis temperature of the first precursor gas, to the substrate; and (c) supplying a reaction gas, which contains the second element that is different from the first element, to the substrate.Type: GrantFiled: September 15, 2020Date of Patent: October 18, 2022Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Ryota Kataoka, Hiroaki Hiramatsu, Kiyohisa Ishibashi