Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.

Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Abstract: A method for forming a silicon dioxide film and a method for forming a metal gate are provided. The method for forming a silicon dioxide film includes: forming a silicon dioxide layer on a semiconductor substrate, performing a nitrogen treatment to the silicon dioxide layer to convert the silicon dioxide layer of partial thickness into a mixed layer of silicon nitride and silicon oxynitride; and removing the mixed layer to form a silicon dioxide film on the semiconductor substrate.

Abstract: Implementations of methods of forming a metal layer on a semiconductor wafer may include: placing a semiconductor wafer into an evaporator dome and adding a material to a crucible located a predetermined distance from the semiconductor wafer. The semiconductor wafer may include an average thickness of less than 39 microns. The method may also include heating the material in the crucible to a vapor and depositing the material on a second side of the semiconductor wafer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Abstract: A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the f

Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.

Abstract: Provided are a method of depositing a thin film and a method of manufacturing a semiconductor device using the same, and the method of depositing a thin film uses a substrate processing apparatus including a chamber, a substrate support on which a substrate is mounted, a gas supply unit, and a power supply unit that supplies high-frequency and low-frequency power to the chamber, and includes: a step of mounting, on the substrate support, the substrate including a lower thin film deposited under the condition of a process temperature in a low temperature range; a step of depositing an upper thin film on the lower thin film under the condition of the process temperature in the low temperature range; and a step of treating a surface of the upper thin film under the condition of the process temperature in the low temperature range.

Abstract: A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.

Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-oxygen-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency less than 15 MHz (e.g., 13.56 MHz). The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.5 and a hardness greater than about 3 Gpa.

Abstract: Exemplary methods of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The methods may include forming a first silicon layer overlying the first silicon oxide layer. The methods may include forming a silicon nitride layer overlying the first silicon layer. The methods may include forming a second silicon layer overlying the silicon nitride layer. The methods may include forming a second silicon oxide layer overlying the second silicon layer. The methods may include removing the silicon nitride layer. The methods may include removing the first silicon layer and the second silicon layer. The methods may include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.

Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming a parent pattern, forming an upper thin film on the parent pattern, forming a child pattern on the upper thin film, measuring a diffraction light from the parent and child patterns to obtain an intensity difference curve of the diffraction light versus its wavelength, and performing an overlay measurement process on the parent and child patterns using the diffraction light, which has the same wavelength as a peak of the intensity difference curve located near a peak of reflectance of the parent and child patterns, to obtain an overlay measurement value.

Abstract: An economical, efficient, and effective formation of a high resolution pattern of conductive material on a variety of films by polymer casting. This allows, for example, quite small-scale patterns with sufficient resolution for such things as effective microelectronics without complex systems or steps and with substantial control over the characteristics of the film. A final end product that includes that high resolution functional pattern on any of a variety of substrates, including flexible, stretchable, porous, biodegradable, and/or biocompatible. This allows, for example, highly beneficial options in design of high resolution conductive patterns for a wide variety of applications.

Abstract: A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.

Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.

Abstract: This work develops a novel microfluidic method to fabricate conductive graphene-based 3D micro-electronic circuits on any solid substrate including, Teflon, Delrin, silicon wafer, glass, metal or biodegradable/non-biodegradable polymer-based, 3D microstructured, flexible films. It was demonstrated that this novel method can be universally applied to many different natural or synthetic polymer-based films or any other solid substrates with proper pattern to create graphene-based conductive electronic circuits. This approach also enables fabrication of 3D circuits of flexible electronic films or solid substrates. It is a green process preventing the need for expensive and harsh postprocessing requirements for other fabrication methods such as ink-jet printing or photolithography. We reported that it is possible to fill the pattern channels with different dimensions as low as 10×10 ?m. The graphene nanoplatelet solution with a concentration of 60 mg/mL in 70% ethanol, pre-annealed at 75° C. for 3 h, provided ˜0.