Abstract: Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.

Abstract: This disclosure relates to dielectric film forming compositions containing a) at least one fully imidized polyimide polymer; b) at least one metal-containing (meth)acrylates; c) at least one catalyst; and d) at least one solvent, as well as related processes and related products. The compositions can form a dielectric film that generates substantially no debris when the dielectric film is patterned by laser ablation process.

Abstract: The present invention provides a ceramic metal circuit board including a ceramic substrate and metal plates bonded to both surfaces of the ceramic substrate through respective bonding layers, wherein a metal film is provided on a surface of one metal plate bonded to one surface of the ceramic substrate; and at least a part of another metal plate bonded to another surface of the ceramic substrate is not provided with the metal film. Preferably, a protruding portion is formed as a portion of the bonding layer so as to protrude from a side surface of each of the metal plates. According to the above-described configuration, it is possible to provide a ceramic circuit board which is easy to use according to the parts to be bonded and is excellent in heat-cycle resistance characteristics.

Abstract: According to one embodiment, an etching apparatus for etching a semiconductor with an aid of a noble metal catalyst, includes a reaction vessel configured to accommodate a semiconductor substrate provided with a catalyst layer including a noble metal, and a feeder configured to feed, to the reaction vessel, an oxidizer, hydrogen fluoride, an organic additive, and carbon dioxide in a supercritical or subcritical state.

Abstract: A semiconductor device includes a first semiconductor module and a second semiconductor module. The first semiconductor module configures an upper arm, and includes first semiconductor elements connected in parallel to each other, a sealing resin body, and a positive electrode terminal. The second semiconductor module configures a lower arm, and includes second semiconductor elements connected in parallel to each other, a sealing resin body, and a negative electrode terminal. The first and second semiconductor modules are aligned in an alignment direction. At least one of the first and second semiconductor modules has a relay terminal for electrically relaying electrodes on a low potential side of the first semiconductor elements and electrodes on a high potential side of the second semiconductor elements.

Abstract: An electroluminescent display apparatus includes a substrate including a display area and a non-display area which surrounds the display area, a crack detecting unit on the substrate in the non-display area, an interlayer insulating layer disposed so as to cover the crack detecting unit, a power supply electrode which is located on the interlayer insulating layer and is disposed between the crack detecting unit and the display area, a protective layer disposed so as to cover the power supply electrode; a planarizing layer which is located on the protective layer and is disposed so as to overlap the crack detecting unit, and an alignment reference unit which is located on the planarizing layer and overlaps the crack detecting unit.

Abstract: A lighting apparatus using an organic light emitting diode comprises a first anode and a second anode respectively disposed in an emission zone and a non-emission zone of an emission area defined at a substrate; a first insulating layer disposed on the second anode; an organic layer and a primary cathode disposed on the first anode; a secondary cathode disposed on the insulating layer and laterally connected to the primary cathode; and an encapsulating material disposed above the substrate, wherein the organic layer is disposed only between the primary cathode and the secondary cathode in the emission zone.

Abstract: A method for lithiation of an electrode includes providing a roll including an electrode to be lithiated, providing a piece of lithium metal with predetermined weight attached to a conductive material, attaching the conductive material to a current collector of the electrode to be lithiated or to a metal tab connected to or from the electrode to be lithiated, placing the roll, the piece of lithium, and the conductive material in a container, and filling the container with an electrolyte containing a lithium salt.

Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin extending above an isolation region. A sacrificial gate is formed over the fin. A first dielectric material is selectively deposited on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate. The fin is patterned using the sacrificial gate and the spacers as a combined mask to form a recess in the fin. An epitaxial source/drain region is formed in the recess.

Abstract: A boron nitride, boron carbide, or boron carbonitride film can be deposited using a remote plasma chemical vapor deposition (CVD) technique. A boron-containing precursor is provided to a reaction chamber, where the boron-containing precursors has at least one boron atom bonded to a hydrogen atom. Radical species, such as hydrogen radical species, are provided from a remote plasma source and into the reaction chamber at a substantially low energy state or ground state. A hydrocarbon precursor may be flowed along with the boron-containing precursor, and a nitrogen-containing plasma species may be introduced along with the radical species from the remote plasma source and into the reaction chamber. The boron-containing precursor may interact with the radical species along with one or both of the hydrocarbon precursor and the nitrogen-containing precursor to deposit the boron nitride, boron carbide, or boron carbonitride film.

Abstract: Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.

Abstract: Plasma atomic layer deposition (ALD) is optimized through modulation of the gas residence time during an excited species phase, wherein activated reactant is supplied such as from a plasma. Reduced residence time increases the quality of the deposited layer, such as reducing wet etch rates, increasing index of refraction and/or reducing impurities in the layer. For example, dielectric layers, particularly silicon nitride films, formed from such optimized plasma ALD processes have low levels of impurities remaining from the silicon precursor.

Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.

Abstract: Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.

Abstract: A light emitting element is disclosed. The light emitting element includes: a mount substrate on which a first electrode pad, a second electrode pad, a third electrode pad, and a fourth electrode pad are disposed; a first vertical LED chip mounted on the mount substrate such that the bottom portion of the first vertical LED chip is connected to the first electrode pad; a second vertical LED chip mounted on the mount substrate such that the bottom portion of the second vertical LED chip is connected to the second electrode pad; a third vertical LED chip mounted on the mount substrate such that the bottom portion of the third vertical LED chip is connected to the third electrode pad; a light-transmitting conductive plate electrically connected to the top portions of the first vertical LED chip, the second vertical LED chip, and the third vertical LED chip; and a conductor connecting the light-transmitting conductive plate to the fourth electrode pad.

Abstract: Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.

Abstract: A solar cell can include a semiconductor substrate; a tunneling layer formed over the semiconductor substrate; a conductive area located over the tunneling layer, the conductive area including a first conductive area of a first conductive type and a second conductive area of a second conductive type; and an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area, wherein a mark is located in at least one of the first conductive area and the second conductive area, and has a different shape from that of a crystal plane of the semiconductor substrate and the conductive area, and wherein the mark is formed along a longitudinally extending edge of at least one of the first conductive area and the second conductive area.

Abstract: A lower electrode, an upper electrode provided above the lower electrode, a semiconductor chip provided between the lower electrode and the upper electrode, a pressure pad provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip, and a spiral conductor provided between the lower electrode and the upper electrode to be overlapped with the semiconductor chip and the pressure pad are provided. The spiral conductor has an upper spiral conductor, and a lower spiral conductor which is in contact with a lower end of the upper spiral conductor and faces the upper spiral conductor, and by forming grooves in the upper spiral conductor and the lower spiral conductor, a direction of a current flowing through the upper spiral conductor coincides with a direction of a current flowing through the lower spiral conductor in plan view.

Abstract: In an end portion of a trench, an opening where the end portion of the trench is exposed is formed in a lead-out electrode, a side surface of the trench gate electrode on a top surface side of a semiconductor substrate is spaced from a trench side surface, and a range adjacent to a boundary line positioned between a top surface of the semiconductor substrate and the trench side surface is covered with a laminated insulating film configured such that an interlayer insulating film is laminated on a gate insulating film. This makes it possible to prevent dielectric breakdown of an insulating film.