Abstract: In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Abstract: Built-in electrical test structures are measured for lead-to-lead shorting during the fabrication of MR elements on a wafer. The test structures are fabricated in the same fashion as the MR elements, however, the active sensor region or track width is omitted from the test structures. Thus, the left and right leads for each test structure are electrically isolated from each other in their “track width” region. If there is lead-to-lead shorting on a test structure, then the left and right leads are electrically connected in the track width region. A simple resistance measurement between the left and right leads determines the extent of any lead shorting by giving a quantitative resistance value.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: Methods and systems for authenticating the operation of electronic devices, such as RFID tags are provided. In accordance with the method, a web of substrates having a plurality of devices attached thereto are received. The operation of a first set of the plurality of devices is authenticated. If it is determined that one or more devices is not operating properly, the location of each device is determined. The web of substrates is then moved incrementally to expose a second set of the plurality of devices. Each device that does not operate properly is indicated by applying ink to the substrate containing the device or by removing the device.

Abstract: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

Abstract: A semiconductor die package having an elastomeric substrate with a first support frame and a second support frame. The first support frame has a cavity within which a semiconductor die is placed. The second support frame may have an optional cavity. The optional cavity in the second support frame may have an optional rigid structure. The rigid structure may have a heating element formed within it.

Abstract: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer insulating layer for the component. An adhesive layer in physical contact with the conductors attaches the circuit decal to the stiffener, and electrically insulates the conductors from the stiffener. The component also includes an area array of terminal contacts on the conductors electrically isolated by the mask layer. A method for fabricating the component includes the steps of attaching the circuit decal to the stiffener, attaching the die to the stiffener, interconnecting the die and the circuit decal, encapsulating the die, and forming the terminal contacts.

Abstract: The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.

Abstract: Systems and methods are described for identifying characteristics and defects in material such as semiconductors. Methods include scanning a thermal probe in the vicinity of a semiconductor sample, applying stimuli to the thermal probe, and monitoring the interaction of the thermal probe and the semiconductor. The stimulus can be applied by a variety of methods, including Joule heating of a resistor in the proximity of the probe tip, or optically heating a tip of the thermal probe using a laser. Applications of the invention include identification of voids in metallic layers in semiconductors; mapping dopant concentration in semiconductors; measuring thickness of a sample material; mapping thermal hot spots and other characteristics of a sample material.

Abstract: According to one aspect of the present invention, a semiconductor device, comprising a wiring board provided with wires and electrodes; a semiconductor element which is mounted on the wiring board and has plural connection electrodes formed on its surface; and a metal layer of fine metal particles aggregated and bonded which is interposed between the electrodes on the wiring board and the connection electrodes of the semiconductor element to connect between the electrodes and the connection electrodes, is provided.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.

Abstract: A method of transfer molding, wherein a top-half mold and a bottom-half mold of an apparatus form a plurality of cavities interconnected, and wherein a pressure adjuster reduces the pressure of the cavities every time a specified amount of resin is supplied into any one of a plurality of cavities.

Abstract: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.

Abstract: A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of forming an alignment post on the substrate before the first step, the alignment post being used for positioning the chip connection wiring.

Abstract: A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

Abstract: Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bottom surface of the substrate. The disclosed embodiment further comprises at least one via in the substrate, which provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via also electrically connects a substrate bond pad and the printed circuit board. The substrate bond pad is further connected to the signal bond pad of the semiconductor die by a signal bonding wire. The at least one via further provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

Abstract: A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conductive tabs are disposed on the stepped tier, and electrically conductive external bond terminals are disposed on an edge of the substrate. Electrically conductive paths are formed in the substrate and electrically coupled between the electrically conductive tabs, the electrically conductive contacts, and the electrically conductive external bond terminals.

Abstract: In accordance with the teachings of the present invention, a semiconductor device having voltage output function trim circuitry and a method for the same are provided. In a particular embodiment, the method includes electrically coupling to a main circuit of a semiconductor device a plurality of resistances each operable to determine a different output voltage range of the main circuit, electrically coupling each of the plurality of resistances to a respective one of a plurality of fuses, electrically coupling each of a plurality of fuses to a respective one of a plurality of function trim pads, and electrically decoupling all but one of the plurality of resistances by applying a respective current between the respective function trim pads and an output node sufficient to open the respective fuses.

Abstract: It is the object of the present invention to provide a manufacturing method for a compound semiconductor device capable of removing remaining organic substances without deteriorating a characteristic of the compound semiconductor device, wherein a surface of an i-type AlGaAs schottky layer is cleaned in a state where light is blocked using either one of ozonized (O3) water whose ozone concentration is at most 13 mg/L and hydrogenated (H2) water whose hydrogen ion concentration (pH) is from 6 to 8 inclusive, or using both of the ozonized water and the hydrogenated water after a schottky electrode made of Ti/Al/Ti is evaporated onto the exposed i-type AlGaAs schottky layer and a lift-off operation is performed using a remover.