Abstract: A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.

Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure.

Abstract: The present invention is directed to a method forming conductive templates that includes providing a substrate; forming a mesa on the substrate; and forming a plurality of recessions and projections on the mesa with a nadir of the recessions comprising electrically conductive material and the projections comprising electrically insulative material. It is desired that the mesa be substantially transparent to a predetermined wavelength of radiation, for example ultraviolet radiation. As a result, it is desired to form the electrically conductive material from a material that allows ultraviolet radiation to propagate therethrough. In the present invention indium tin oxide is a suitable material from which to form the electrical conductive material.

Abstract: A method of determining wafer curvature in real-time is presented. The method includes establishing a first temperature profile for a hotplate surface, where the hotplate surface is divided into a plurality of temperature control zones. The method further includes positioning a wafer at a first height above the hotplate surface and determining a second temperature profile for the hotplate surface. The wafer curvature is then determined by using the second temperature profile. Also, a dynamic model of a processing system is presented and wafer curvature can be incorporated into the dynamic model.

Abstract: An electronic device includes a semiconductor chip storing an identification number of N-bits and an antenna coupled to the semiconductor chip that sends out the identification number of N-bits. In order to provide a secure and efficient data storage arrangement, the identification number of N-bits is stored in accordance with the presence or absence of through holes that connect wirings to transistors included in the semiconductor chip through an insulating film formed over the transistors.

Abstract: One or more simulated diffraction signals for use in determining the profile of a structure formed on a semiconductor wafer can be generated, where the profile varies in more than one dimension. Intermediate calculations are generated for variations in a hypothetical profile of the structure in a first dimension and a second dimension, where each intermediate calculation corresponds to a portion of the hypothetical profile of the structure. The generated intermediate calculations are then stored and used in generating one or more simulated diffraction signals for one or more hypothetical profiles of the structure.

Abstract: This invention provides methods for predictively revealing, in bulk silicon substrates, latent crystalline defects in bulk silicon substrates that become apparent only after subsequent processing, e.g., after processing during which multiple layers are split and lifted from the bulk substrates. Preferred predictive methods include a revealing heat treatment of bulk substrates conducted in a non-reducing atmosphere at a temperature in the range from approximately 500° C. to 1300° C. If desired, a further revealing heat treatment or defect enlargement step can be performed to enlarge defects revealed by the first revealing heat treatment.

Abstract: A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

Abstract: A method is provided for selectively marking a region of integrated circuit (IC). The method provides an IC die with a first region located on a backside surface of a bulk silicon (Si) layer. A semi-transparent film is formed overlying the bulk Si layer, semi-transparent to light having a first wavelength. The semi-transparent film is irradiated with light having the first wavelength in the range of 1 to 2 microns. In response to irradiating the semi-transparent film with a first power density, the IC die first region is located. Then, in response to irradiating the semi-transparent film with a second power density, greater than the first power density, a region of the semi-transparent film is marked overlying the IC die first region. In one aspect, a region of the bulk Si layer underlying the marked (or ablated away) semi-transparent film is selectively etched to expose the IC die first region.

Abstract: Bright and dark field imaging operations in an optical inspection system occur along substantially the same optical path using the same light source by producing either a circular or an annular laser beam. Multiple beam splitting is achieved through the use of a diffractive optical element having uniform diffraction efficiency. A confocal arrangement for bright field and dark field imaging can be applied with multiple beam scanning for suppressing the signal from under-layers. A scan direction not perpendicular to the direction of movement of a target provides for improved die-to-die comparisons.

Abstract: A system for identifying systematic yield losses comprises a device configured to test produced products using a test sequence that produces yield data related to a wafer. The wafer is divided into multiple zones. Series of yield data may be collected and stored for each zone. A first data series R1 is the yield of a zone; a second data series R2 is a p consecutive element moving average of data series R1; and a third data series R3 is a p consecutive element moving standard deviation of data series R1. A device is configured to calculate a trigger point for each element of R1, wherein the trigger point is calculated as the respective R2 element less an adjusted respective R3 value. A notification may be provided to a user when the trigger point calculated for each element of R1 is greater than the respective element of R1.

Abstract: A semiconductor element heat dissipating member is provided which has excellent heat dissipation characteristics and adhesion characteristics and enables production of a semiconductor device at a low cost. A semiconductor device using the same, and a method of producing the same are also provided. The semiconductor element heat dissipating member has a conductive substrate and an electrically insulating amorphous carbon film containing hydrogen, and the electrically insulating amorphous carbon film is formed at least on a region of the conductive substrate on which region a semiconductor element is to be mounted.

Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.

Abstract: An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device layer on the wafer, whereby both patterns can be printed in a single photolithographic operation. The same oxidation process used to produce an isolating oxide between active device regions of the active device layer can also be used to produce the positional reference structure.

Abstract: An integrated circuit packaging device includes a laminate substrate. A first surface of the substrate can be mounted on an integrated circuit and the second surface can be mounted on a surface of a printed circuit board. The device can also include an array of lead contact pads on the first surface that can provide wire bond connections to circuit contact pads in the integrated circuit, and an array of solder ball contact pads on the second surface. Routing layers can provide electrical coupling between the lead contact pads on the first surface and the solder ball contact pads on the second surface. A dedicated contact pad on the first surface is electrically coupled to the laminate substrate.

Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.

Abstract: A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.

Abstract: A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a plurality of contact pads on a PCB. At least one of a plurality of solder balls of an IC device are then onto the at least one of the plurality of contact pads on the PCB. The temperature is then increased to reflow the solder paste. The IC device is then pulled away from the PCB as a function of a geometric shape of the IC device and held in a new position upon reflowing the solder paste to transform the at least one of the plurality of solder balls and the reflowed solder paste into a high shear strength solder joint structure. The reflow temperature is then lowered to room temperature to attach the high shear strength solder joint structure to the at least one of the plurality of lands on the PCB.

Abstract: A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include one or more recessed areas that laterally surround at least a portion of the die-attach location to receive excess adhesive.