Patents Examined by Andre? Stevenson
  • Patent number: 10319682
    Abstract: An electronic component device includes a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface, at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by joining the terminal electrode to the mount electrode, and a sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted. The sealing resin layer includes a region with a large thickness, and a top surface including an inclination.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 11, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazushi Watanabe
  • Patent number: 10312469
    Abstract: A display device includes: a substrate including a display area and a non-display area outside the display area; a display unit arranged in the display area of the substrate; an inorganic insulating film arranged on the substrate over the display area and the non-display area; a first organic insulating film arranged on the inorganic insulating film and having a first opening extending in a first direction so as to correspond to at least a portion of the non-display area, a planar shape of an end of the first opening having a concavo-convex shape; and an encapsulation unit arranged on the display unit to cover the display unit.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 4, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunae Park, Wonkyu Kwak, Jieun Lee
  • Patent number: 10297624
    Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Kunikiyo, Hidenori Sato, Yotaro Goto, Fumitoshi Takahashi
  • Patent number: 10270018
    Abstract: Disclosed is a light emitting diode including a side reflection layer. The light emitting diode includes a substrate having a side surface and an upper surface; a semiconductor stack disposed under the substrate and including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; an ohmic reflection layer electrically connected to the second conductivity type semiconductor layer; a first bump pad disposed under the ohmic reflection layer and electrically connected to the first conductivity type semiconductor layer; a second bump pad disposed under the ohmic reflection layer and electrically connected to the second conductivity type semiconductor layer; a side reflection layer covering the side surface of the substrate; and a capping layer covering the upper surface of the substrate and the side reflection layer.
    Type: Grant
    Filed: January 7, 2018
    Date of Patent: April 23, 2019
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Youn Kim, Jae Hee Lim
  • Patent number: 10261348
    Abstract: A display device according to the present disclosure may be provided with a light path conversion protrusion on a lower surface of a cover window to suppress external light even for light incident at a side viewing angle, thereby improving contrast and visibility. According to the present disclosure, side-view angle incident light may be converted into the same incident light as that of vertical incident light, thereby providing an effect capable of preventing the reflection of incident light from a viewing angle as well as the vertical incident light.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Wonjong Cho, Daeheung Lee, Wonki Park
  • Patent number: 10256392
    Abstract: Techniques for a vertical transmon qubit device are provided. In one embodiment, a chip surface base device structure is provided that comprises a first superconducting material physically coupled to a crystalline substrate, wherein the crystalline substrate is physically coupled to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt, Rasit Onur Topaloglu
  • Patent number: 10256395
    Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the sidewalls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Daniel R. Lamborn, Oleg Golonzka, Christopher J. Wiegand, Philip E. Heil, M D Tofizur Rahman, Rebecca J. Castellano, Tarun Bansal
  • Patent number: 10247630
    Abstract: A semiconductor device includes a metal body; a bonding layer placed on the metal body; and a semiconductor chip placed on the bonding layer. The bonding layer includes a filler-containing first layer formed between the metal body and the semiconductor chip and a second layer bonded to the first layer and the semiconductor chip. The second layer has a thermal expansion coefficient higher than that of the first layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 2, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Hanae Shimokawa, Shosaku Ishihara, Atsuo Soma, Junji Onozuka, Hiroshi Onuki, Daisuke Terada, Mizuki Shibata
  • Patent number: 10249639
    Abstract: A semiconductor memory device according to an embodiment includes: first and second memory columnar bodies aligned in a second direction intersecting a first direction, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction; a bit line disposed above the first and second memory columnar bodies; and a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line, the first connecting line extending linearly in the second direction, and a center line widthwise of the first connecting line being in a position displaced in a third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshiro Shimojo
  • Patent number: 9887350
    Abstract: A hard mask stack for etching a magnetic tunneling junction (MTJ) structure is described. An electrode layer is deposited on a stack of MTJ layers on a bottom electrode. A photoresist mask is formed on the electrode layer. The electrode layer is etched away where it is not covered by the photoresist mask to form a metal hard mask. The metal hard mask is passivated during or after etching to form a smooth hard mask profile. Thereafter, the photoresist mask is removed and the MTJ structure is etched using the metal hard mask wherein the metal hard mask remaining acts as a top electrode. The resulting MTJ device has smooth sidewalls and uniform device shape.
    Type: Grant
    Filed: May 31, 2015
    Date of Patent: February 6, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Dongna Shen, Yu-Jen Wang, Jesmin Haq
  • Patent number: 8679972
    Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Michal Danek, Erich Klawuhn
  • Patent number: 8062955
    Abstract: A CoWB film is formed as a cap metal on a Cu interconnection line formed on a substrate or wafer W, by repeating a plating step and a post-cleaning step a plurality of times. The plating step is arranged to apply electroless plating containing CoWB onto the Cu interconnection line. The post-cleaning step is arranged to clean the wafer W by use of a cleaning liquid, after the plating step.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: November 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Tanaka, Kenichi Hara, Mitsuaki Iwashita
  • Patent number: 8034685
    Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shield electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shield electrodes. A gate electrode in at least one of the trenches is connected to at least one shield electrode in the trenches.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: October 11, 2011
    Assignee: Semiconductor Component Industries, LLC
    Inventors: Prasad Venkatraman, Zia Hossain, Kirk K. Huang
  • Patent number: 8030157
    Abstract: A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Habib Hichri, Ahmad D. Katnani, Kaushik A. Kumar, Narender Rana, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff
  • Patent number: 7851250
    Abstract: An object is to provide a method for manufacturing a highly-reliable semiconductor device with an improved material use efficiency and with a simplified manufacturing process. The method includes the steps of forming a conductive layer over a substrate, forming a light-transmitting layer over the conductive layer, and selectively removing the conductive layer and the light-transmitting layer by irradiation with a femtosecond laser beam from above the light-transmitting layer. Note that the conductive layer and the light-transmitting layer may be removed so that an end portion of the light-transmitting layer is located on an inner side than an end portion of the conductive layer. Before the irradiation with a femtosecond laser beam, a surface of the light-transmitting layer may be subjected to liquid-repellent treatment.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masafumi Morisue, Koichiro Tanaka
  • Patent number: 7601555
    Abstract: A wafer inspection system includes an electrical testing part to control a probe to be in contact with a pad of a wafer to perform a predetermined electrical test, a defect detecting part to detect a defect in the wafer passing through the electrical test, a defect sorting part to sort the defect detected in the defect detecting part by an in-line method, and a defective determining part to determine whether the wafer is a defective according to a sorting result of the defect sorting part. The wafer inspection system and a method thereof can determine the kinds of the defect in the wafer during a fabricating procedure, so that it is possible to instantly and correctly determine whether the die on the wafer is a defective.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: October 13, 2009
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kwang-soo Kim, Koung-su Shin, Seung-min Choi, Yu-han Jeong
  • Patent number: 7534629
    Abstract: By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: May 19, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Teruo Shoji, Akio Hasebe, Yoshinori Deguchi, Motoji Murakami, Masayoshi Okamoto, Yasunori Narizuka, Susumu Kasukabe
  • Patent number: 7528937
    Abstract: An apparatus for measuring the relative positions of frontside and backside alignment marks located on opposite sides of a substrate is disclosed. The apparatus includes upper and lower optical systems that allow for simultaneous imaging of frontside and backside alignment marks. The frontside and backside alignment mark images are processed to determine the relative position of the marks, as a measurement of the alignment and/or overlay performance of the tool that formed the marks on the substrate.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: May 5, 2009
    Assignee: Ultratech, Inc.
    Inventors: Albert J. Crespin, Jim Woodruff, Ray Ellis, Scott Kulas, Joe Jamello, Emily True
  • Patent number: 7508081
    Abstract: The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer (2) on a substrate material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein the adhesion of the pressure-sensitive adhesive layer (2) to the die-bonding adhesive layer (3), as determined under the conditions of a peel angle of 15° and a peel point moving rate of 2.5 mm/sec. at 23° C., is different between a region (2a) corresponding to a work attachment region (3a) and a region (2b) corresponding to a part or the whole of the other region (3b), in the die-bonding adhesive layer (3), and satisfies the following relationship: adhesion of the pressure-sensitive adhesive layer (2a)<adhesion of the pressure-sensitive adhesive layer (2b), and the adhesion of the pressure-sensitive adhesive layer (2a) to the die-bonding adhesive layer (3) is not higher than 2.3 N/25 mm.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: March 24, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Takeshi Matsumura, Masaki Mizutani, Sadahito Misumi
  • Patent number: 7497911
    Abstract: Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates and flex films through various manufacturing processes. The flexible substrate is bonded to a rigid carrier. The carrier is placed into a specialized fixture comprising a bottom plate and a top plate. The bottom plate with raised regions is created that allows the windowed region of the flex film to be pressed flat. After aligning the top plate, the bottom plate, and the middle structure, the plates are pressed together causing the raised regions to push the flex film substrate upward and around the carrier.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: March 3, 2009
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Anthony A. Primavera, Vijesh Unnikrishnan, David J. Smith