Abstract: In the methods of compensating for an alignment error during fabrication of structures on semiconductor substrates, a conductive pattern structure is formed at a first position on a first semiconductor substrate. The conductive pattern structure includes a grid of first and second conductive patterns arranged as columns and intersecting rows with openings bounded therebetween. A first conductive contact structure overlaps the conductive pattern structure, and includes a plurality of spaced apart conductive contacts arranged as a grid of rows and columns that can be tilted at a non-zero angle relative to the grid of the conductive pattern structure. A determination is made as to whether the first conductive contact structure is electrically connected to the conductive pattern structure.

Abstract: A method of measuring warpage of a rear surface of a substrate includes a substrate detection step, a best fit plane calculation step, and a warpage calculation step. Further, the method of measuring warpage of a rear surface of a substrate can further includes after the substrate detection step and before the best fit plane calculation step: a noise removal step and an outer peripheral portion removal step; the outer peripheral portion removal step and a smoothing step; or the noise removal step, the outer peripheral portion removal step, and the smoothing step. Thereby, a method of measuring warpage of a rear surface with a high surface roughness of a substrate can be provided.

Abstract: The present invention is directed to a method forming conductive templates that includes providing a substrate; forming a mesa on the substrate; and forming a plurality of recessions and projections on the mesa with a nadir of the recessions comprising electrically conductive material and the projections comprising electrically insulative material. It is desired that the mesa be substantially transparent to a predetermined wavelength of radiation, for example ultraviolet radiation. As a result, it is desired to form the electrically conductive material from a material that allows ultraviolet radiation to propagate therethrough. In the present invention indium tin oxide is a suitable material from which to form the electrical conductive material.

Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side.

Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.

Abstract: A packaging method for segregating die paddles of a leadframe, includes (a) providing a leadframe having a top surface, a bottom surface and a die paddle region, the die paddle region having a plurality of die paddles, wherein at least two of the die paddles are connected to each other by at least one connecting bar; (b) attaching a plurality of dies onto the die paddles; (c) forming a molding compound to encapsulate the dies on the die paddles, and exposing the bottom surface of the connecting bar outside the molding compound; and (d) removing part of the connecting bar so as to segregate the die paddles. The die paddles are thus rendered stable during the steps of die attaching, wire bonding and molding, and the yield is raised.

Abstract: A method of determining wafer curvature in real-time is presented. The method includes establishing a first temperature profile for a hotplate surface, where the hotplate surface is divided into a plurality of temperature control zones. The method further includes positioning a wafer at a first height above the hotplate surface and determining a second temperature profile for the hotplate surface. The wafer curvature is then determined by using the second temperature profile. Also, a dynamic model of a processing system is presented and wafer curvature can be incorporated into the dynamic model.

Abstract: In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

Abstract: Disclosed is a method of measuring a pattern shift in a semiconductor device. The method measures a mobility or shift distance of a stepped portion occurring between a buried layer surface and a substrate surface during an epitaxial process on the buried layer. The method includes the steps of: recognizing a first width ratio of a metallic wiring over a stepped pattern in an insulation film shifted by a certain distance and measuring a first capacitance value of a capacitor including the metallic wiring, forming a first pattern having a second width ratio different from the first width ratio, measuring a capacitance value of the first pattern, forming multiple patterns having width ratios different from the first and second width ratios, measuring capacitance values of the multiple patterns, establishing reference values using the measured capacitance values, and comparing the first capacitance value with any one of the established reference values to recognize a shift distance of the stepped pattern.

Abstract: An electronic device includes a semiconductor chip storing an identification number of N-bits and an antenna coupled to the semiconductor chip that sends out the identification number of N-bits. In order to provide a secure and efficient data storage arrangement, the identification number of N-bits is stored in accordance with the presence or absence of through holes that connect wirings to transistors included in the semiconductor chip through an insulating film formed over the transistors.

Abstract: A correlation between develop inspect (DI) and final inspect (FI) profile parameters are established empirically with test wafers. During production, a wafer is measured at DI phase to obtain DI profile parameters and FI phase profile parameters are predicted according to the DI profile parameters and the established correlation. Each wafer is subsequently measured at FI phase to obtain actual FI profile parameters and the correlation is updated with actual DI and FI profile parameters.

Abstract: The integrated circuitry on a semiconductor substrate includes an integrated circuit arranged in a circuit area of the semiconductor substrate and a stress-sensitive structure on the semiconductor substrate for detecting a mechanical stress component in the semiconductor substrate, wherein the stress-sensitive structure is implemented to provide an output signal depending on the mechanical stress component in response to an excitation and to a mechanical stress component, wherein the stress-sensitive structure is arranged in a sensor area of the semiconductor substrate and wherein the circuit area and the sensor area are spatially separated.

Abstract: One or more simulated diffraction signals for use in determining the profile of a structure formed on a semiconductor wafer can be generated, where the profile varies in more than one dimension. Intermediate calculations are generated for variations in a hypothetical profile of the structure in a first dimension and a second dimension, where each intermediate calculation corresponds to a portion of the hypothetical profile of the structure. The generated intermediate calculations are then stored and used in generating one or more simulated diffraction signals for one or more hypothetical profiles of the structure.

Abstract: A method for forming a redistribution layer in a wafer structure, including (a) providing a wafer having a plurality of conductive structures and a first passivation layer thereon, wherein the first passivation layer covers the wafer except the conductive surfaces of the conductive structures; (b) forming a second passivation layer over the first passivation layer; (c) selectively removing part of the second passivation layer to form a plurality of grooves corresponding to a predetermined circuit; (d) forming a redistribution layer in the grooves; and (e) forming a third passivation layer over the second passivation layer and the redistribution layer. As a result, the redistribution layer is “embedded” in the second passivation layer so as to avoid the delamination of the redistribution layer.

Abstract: A method of manufacturing a semiconductor device includes (a) fixing a cover onto a semiconductor substrate so as to place a surface of the cover that includes a portion defining a first opening, face to face on a surface of the semiconductor substrate that includes an electrode and (b) applying an adhesive to the inside of the first opening.

Abstract: This invention provides methods for predictively revealing, in bulk silicon substrates, latent crystalline defects in bulk silicon substrates that become apparent only after subsequent processing, e.g., after processing during which multiple layers are split and lifted from the bulk substrates. Preferred predictive methods include a revealing heat treatment of bulk substrates conducted in a non-reducing atmosphere at a temperature in the range from approximately 500° C. to 1300° C. If desired, a further revealing heat treatment or defect enlargement step can be performed to enlarge defects revealed by the first revealing heat treatment.

Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.

Abstract: During probe testing using a prober having probe needles formed by using a manufacturing technology for a semiconductor integrated circuit device, reliable contact is ensured between the probe needles and test pads. A pressing tool having at least one hole portion formed therein and extending therethrough between the main and back surface thereof is prepared. An elastomer in the form of a sheet and a polyimide sheet are successively disposed on the main surface of the pressing tool. With th elastomer and the polyimide sheet being electrostatically attracted to the pressing tool, the pressing tool is disposed on a thin-film sheet such that the main surface thereof faces the back surface (the surface opposite to the main surface thereof formed with the probe) of the thin-film sheet. Then, the thin-film sheet with the pressing tool bonded thereto is attached to a probe card.

Abstract: A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

Abstract: A method is provided for selectively marking a region of integrated circuit (IC). The method provides an IC die with a first region located on a backside surface of a bulk silicon (Si) layer. A semi-transparent film is formed overlying the bulk Si layer, semi-transparent to light having a first wavelength. The semi-transparent film is irradiated with light having the first wavelength in the range of 1 to 2 microns. In response to irradiating the semi-transparent film with a first power density, the IC die first region is located. Then, in response to irradiating the semi-transparent film with a second power density, greater than the first power density, a region of the semi-transparent film is marked overlying the IC die first region. In one aspect, a region of the bulk Si layer underlying the marked (or ablated away) semi-transparent film is selectively etched to expose the IC die first region.