Patents Examined by Andrew Caldwell
  • Patent number: 10740068
    Abstract: A modular reduction device particularly for cryptography on elliptical curves. The device includes a Barrett modular reduction circuit and a cache memory in which the results of some precalculations are carried out. When the result is not present in the cache memory, a binary division circuit makes the precalculation and stores the result in the cache memory.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 11, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Thomas Hiscock
  • Patent number: 10732972
    Abstract: A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L?1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Razvan Peter Figuli, Stefan Payer, Cedric Lichtenau, Petra Leber
  • Patent number: 10726350
    Abstract: Ripple-carry and carry look-ahead adders for ternary addition and other operations include circuits that produce carry values or carry status indicators that can be stored on qutrit registers associated with input values to be processed. Inverse carry circuits are situated to reverse operations associated with the production of carry values or carry status indicators, and restored values are summed with corresponding carry values to produce ternary sums.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 28, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xingshan Cui, Alexei Bocharov, Martin Roetteler, Krysta Svore
  • Patent number: 10727819
    Abstract: According to one embodiment, an information processing device, includes: a digital-to-pulse converter configured to output a pulse signal including a pulse with a pulse length corresponding to a digital input signal; and a bidirectional selective oscillator including a first ring oscillator and a second ring oscillator, the first ring oscillator including a plurality of delay elements connected in a ring shape in a first direction, the second ring oscillator including a plurality of delay elements connected in a ring shape in a second direction reverse to the first direction. The bidirectional selective oscillator is configured to select one of the first ring oscillator and the second ring oscillator depending on a sign of the digital input signal, oscillate the selected ring oscillator during a period when the pulse is outputted, and keep a state of oscillation operation when the pulse stops being outputted.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Toyama, Kentaro Yoshioka, Kohei Onizuka
  • Patent number: 10713333
    Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Farhana Sheikh, Ankit Sharma, Jaydeep Kulkarni
  • Patent number: 10713013
    Abstract: An apparatus for an exponential function for a half-precision floating-point format for an exponent x includes a denormalizer for receiving sign, exponent and significand bits for conversion of significant bits to a fixed-point format for a signed fixed-point representation. A splicer receives the signed fixed-point representation to output first, second and third splices. A first lookup table receives the first splice for accessing a floating-point exponent and a floating-point mantissa. A second lookup table receives the second splice for accessing a fixed-point exponent value. A first multiplier receives the fixed-point exponent value and the third splice to provide a first multiplication result. An adder receives the fixed-point exponent value and the first multiplication result to provide a sum. A second multiplier receives the floating-point mantissa and the sum to provide a second multiplication result.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventor: Gordon I. Old
  • Patent number: 10698658
    Abstract: Apparatuses and methods disclosed herein relate to detecting a signal generated by a spin torque oscillator (STO). The signal is outputted, wherein the signal includes a direct current (DC) component, a wide bandwidth noise component, and an STO oscillating radio frequency (RF) component. The signal is filtered, wherein the filtering removes the DC component and the STO oscillating RF component, leaving the wide bandwidth noise component. A value of the wide bandwidth noise component is converted into a binary value, and a bit from the binary value is selected and combined with another bit to form a random number.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 30, 2020
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, Lihong Zhang, WenXiang Xie, Quan Li
  • Patent number: 10698973
    Abstract: A method for concurrent reading of mixed radix DFT/IDFT data, a method for concurrent calculation of mixed radix DFT/IDFT method, an apparatus for concurrent reading of mixed radix DFT/IDFT data, and an apparatus for concurrent calculation of mixed radix DFT/IDFT. The method for concurrent reading includes: configuring dual circulation parameters according to the number of points corresponding to the number of series to be computed and the number of points corresponding to the number of series accomplished; then, determining the value size between the maximum number of concurrently read data and the product of the number of points corresponding to the number of series accomplished; and based on the result of determination, calculating the dual circulation parameters corresponding thereto according to the result of determination, and concurrently reading data based on the calculated dual circulation parameters.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 30, 2020
    Assignee: Institute of Automation, Chinese Academy of Sciences
    Inventors: Huan Li, Xiaoqin Wang, Chen Guo
  • Patent number: 10698860
    Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or the arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a line-shaped magnetic part.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 30, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Rie Sato, Hayato Goto, Koichi Mizushima
  • Patent number: 10699209
    Abstract: Quantum algorithms to solve practical problems in quantum chemistry, materials science, and matrix inversion often involve a significant amount of arithmetic operations. These arithmetic operations are to be carried out in a way that is amenable to the underlying fault-tolerant gate set, leading to an optimization problem to come close to the Pareto-optimal front between number of qubits and overall circuit size. In this disclosure, a quantum circuit library is provided for floating-point addition and multiplication. Circuits are presented that are automatically generated from classical Verilog implementations using synthesis tools and compared with hand-generated and hand-optimized circuits. Example circuits were constructed and tested using the software tools LIQUi| and RevKit.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 30, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas Haener, Martin Roetteler, Krysta Svore
  • Patent number: 10691416
    Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 23, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Thomas Rose
  • Patent number: 10691414
    Abstract: A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 23, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Meng-Yi Wu, Hsin-Ming Chen
  • Patent number: 10691411
    Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew?1), bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.
    Type: Grant
    Filed: January 4, 2020
    Date of Patent: June 23, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Kenneth Rovers
  • Patent number: 10684824
    Abstract: A method, computer readable medium, and system are disclosed for rounding numerical values. A set of bits from an input value is identified as a rounding value. A second set of bits representing a second value is extracted from the input value and added with the rounding value to produce a sum. The sum is truncated to produce the rounded output value. Thus, the present invention provides a stochastic rounding technique that rounds up an input value as a function of a second value and a rounding value, both of which were obtained from the input value. When the second value and rounding value are obtained from consistent bit locations of the input value, the resulting output value is deterministic. Stochastic rounding, which is deterministic, is advantageously applicable in deep learning applications.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, Paulius Micikevicius, Hao Wu, Ming Yiu Siu
  • Patent number: 10678509
    Abstract: An example multiply accumulate (MACC) circuit includes a multiply-accumulator having an accumulator output register, a scaler, coupled to the multiply accumulator, and a control circuit coupled to the multiply-accumulator and the scaler. The control circuit is configured to provide control data to the scaler, the control data indicative of: a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register for implementing a first right shift; a multiplier; and a second right shift.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 9, 2020
    Assignee: XILINX, INC.
    Inventors: Sean Settle, Elliott Delaye, Aaron Ng, Ehsan Ghasemi, Ashish Sirasao, Xiao Teng, Jindrich Zejda
  • Patent number: 10671345
    Abstract: An integrated circuit may include normalization circuitry that can be used when converting a fixed-point number to a floating-point number. The normalization circuitry may include at least a floating-point generation circuit that receives the fixed-point number and that creates a corresponding floating-point number. The normalization circuitry may then leverage an embedded digital signal processing (DSP) block on the integrated circuit to perform an arithmetic operation by removing the leading one from the created floating-point number. The resulting number may have a fractional component and an exponent value, which can then be used to derive the final normalized value.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventor: Bogdan Pasca
  • Patent number: 10649732
    Abstract: This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (SC1, SC2) respectively, and generate respective first and second PWM signals (SPWM1, SPWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (SC1) corresponds to a sum of a first and second input signals (S1, S2) and the second combined signal (SC2) corresponds to the difference between the first and second input signals (S1, S2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D1, D2) based on a parameter related to the frequency of the respective first or second PWM signal.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 12, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Mark McCloy-Stevens
  • Patent number: 10649738
    Abstract: A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Klaus M. Kroener, Silvia Melitta Mueller, Andreas Wagner
  • Patent number: 10644677
    Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Shawn Xianggang Yu
  • Patent number: 10642921
    Abstract: Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using shared hardware circuits. The unified architecture exploits the symmetry properties of forward and inverse transform matrices to achieve hardware sharing across the different transform sizes and also between forward and inverse transform computations.
    Type: Grant
    Filed: November 4, 2012
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Madhukar Budagavi