Abstract: An apparatus has a fetch queue to identify a sequence of instructions to be fetched for execution and prediction circuitry to predict upcoming control flow and to control which instructions are identified in the fetch queue in dependence on the prediction. The prediction circuitry predicts multi-taken sequences which are sequences of instructions in which control flow is diverted by a first control flow changing instruction to a series of instructions terminating in a second control flow changing instruction that diverts control flow to a target address. The apparatus also has prediction confidence calculation circuitry to calculate confidence levels for respective multi-taken sequences. Each confidence level is indicative of a confidence in an accuracy of prediction of its respective multi-taken sequence.

Abstract: Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit.

Abstract: A processing unit for multiplying a first value by a first multiplicand, or for multiplying the first value by, in each instance, a second and third multiplicand. The processing unit receives the multiplicands in a logarithmic number format, so that the multiplicands are each present in the form of at least one exponent at a specifiable base. The processing unit includes a first register, in which either two exponents of the first multiplicand or the exponent of the second and the exponent of the third multiplicand are stored. A set configuration bit indicates whether either the two exponents of the first multiplicand or the exponent of the second and the exponent of the third multiplicand are stored in the first register. The processing unit includes at least two bitshift operators. A method and a computer program for multiplying the value by the multiplicand are also described.

Abstract: Rescheduling a load instruction based on past replays is disclosed. A load replay predictor of a processor device determines, at a first time, that a load instruction is scheduled to be executed by a load store unit to load data from a memory location. The load replay predictor accesses load replay data associated with a previous replay of the load instruction and, based on the load replay data, causes the load instruction to be rescheduled.

Abstract: Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described.

Abstract: A dot product array comprises dot product circuits each to process a respective pair of first and second input vectors to generate a respective dot product result. In a real number mode, each dot product result and vector element represents a respective real number. In a hypercomplex number mode, an input vector manipulation is applied to at least one of the first/second input vectors to be supplied to each dot product circuit, to cause the dot product array to generate hypercomplex dot product results each indicating a sum of hypercomplex products of corresponding pairs of hypercomplex numbers. In the hypercomplex number mode, respective subsets of elements of the first/second input vectors represent respective hypercomplex numbers, for which respective components are represented by different elements of the subset, and each hypercomplex dot product result comprises components represented by the dot product results generated by a corresponding group of at least two dot product circuits.

Abstract: An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.

Abstract: An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.

Abstract: Provided are an apparatus and method for generating random numbers based on reinforcement learning. The method is implemented with a computer, and includes: generating a first random number based on a deep learning-based first model through an agent unit; calculating respective similarities between at least one previously stored second random number and the first random number; performing reinforcement learning based on generative behavior of the first random number of the agent unit based on the respective similarities; and storing the first random number in a memory. The performance of the reinforcement learning is configured to provide compensation information based on the respective similarities to the agent unit through an environment unit, and then to control the agent unit to learn the first model based on the first random number.

Abstract: A system and a method for verifying a randomness of an intended random number is provided. The method includes: accessing the intended random number; converting the intended random number into a bitmap image; analyzing the bitmap image with reference to a predetermined model; and using a result of the analyzing to determine whether the intended random number is a true random number or a pseudorandom number. The analysis of the bitmap image may be performed by using a machine learning image classification technique with respect to a model that is trained by using white noise images.

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a first control transfer instruction is mispredicted, a second control transfer instruction may have been executed on the wrong path because of the misprediction. Result storage circuitry may record information indicating a determined direction for the second control transfer instruction. Control flow tracker circuitry may store, for the first control transfer instruction, information indicating a reconvergence point. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine, based on the tracked registers, that the second control transfer instruction does not depend on data from any instruction between the first control transfer instruction and the reconvergence point, and use the recorded determined direction for the second control transfer instruction, notwithstanding the misprediction of the first control transfer instruction.

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

Abstract: The present invention relates to a logic device using skyrmion, which comprises an input part; an output part; and an operation part located between the input part and the output part and includes at least one notch where the skyrmion can be annihilated, and in which the skyrmion moves from the input part to the output part by the applied current. The logic device provided in one aspect of the present invention consumes relatively little power, can have high integration, and has an effect of having a very simple structure compared to the conventional logic device by using the annihilation of skyrmion.

Abstract: A method for performing a pooling operation in bitwise manner, the method includes performing a pooling operation on ternary data upon receiving an input ternary vector, receiving an input binary vector, providing a fused hardware for performing the pooling operation on any of the received binary and the ternary data, and executing the pooling operation performed bitwise through the fused hardware.

Abstract: The present application discloses a data processing method and apparatus, an electronic device, and a computer-readable storage medium. The method is applied to a convolution adaptor, and the convolution adaptor is arranged between external storage and an internal cache of a computing unit. The method includes: acquiring register data, where the register data is determined according to data types of target data and/or convolution types of convolution processing applied to the target data, and is used for describing reading modes of the target data; and reading the target data from the external storage according to the register data, and storing the target data in the internal cache according to a data read sequence.

Abstract: Merging store instructions for a memory includes receiving a first store instruction having a first address, and determining a first pattern based on a comparison of the first address and a second address of an entry within a buffer. Further, a size field of the entry is updated based on the first pattern. The first address of the first store instruction is merged with the second address within the entry to generate a merged instruction. The merged store instruction is communicated to the memory.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

Abstract: A method and system for processing a set of ‘k’ floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of ‘k’ numbers concurrently.

Abstract: An apparatus includes a processor core that includes an instruction decode circuit and a control circuit. The instruction decode circuit is configured to decode instructions, including a plurality of store instructions used to store information in a memory hierarchy. The control circuit is configured, after a particular store instruction is decoded, to preserve store information related to the particular store instruction, including a first program counter value for the particular store instruction. In response to decoding a subsequent load instruction with a corresponding second program counter value, the control circuit is configured to determine, using the first and second program counter values, whether a dependency has been established between the subsequent load instruction and the particular store instruction. In response to a determination that the dependency has been established, the control circuit is configured to use the preserved store information to perform the subsequent load instruction.

Abstract: An information processing apparatus includes a memory and a processor. The processor configured to acquire, among a plurality of solutions, a first solution corresponding to a best value among values of a plurality of the energy functions corresponding to the plurality of solutions, each of the plurality of solutions being represented by a value of each of a plurality of state variables included in an energy function, generate a first state variable string based on the first solution, and search for a solution with the first state variable string as a start state.