Patents Examined by Andrew Caldwell
  • Patent number: 11023205
    Abstract: Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo
  • Patent number: 11023209
    Abstract: An electric device for a hardware random number generator is provided. The hardware random number generator comprises: one or more bitcells which comprise a first pair of a first transistor and a first tunable resistor and a second pair of a second transistor and a second tunable resistor, with the first pair is cross-coupled with the second pair.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 11023208
    Abstract: A true random number generator includes a latch circuit, a noise circuit coupled to the latch circuit and an equalization circuit coupled to the inputs of the latch circuit, the equalization circuit being configured to maintain the latch circuit in a balanced state and to allow the latch circuit to resolve from a metastable state based on a timing control. A method of generating a random number output includes maintaining a latch circuit in a balanced state by turning on an equalization circuit coupled to the inputs of the latch circuit, coupling at least one noise source to the latch circuit, allowing the latch circuit to resolve from a metastable state by turning off the equalization circuit and repeatedly turning the equalization circuit on and off based on a timing control.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chitra K. Subramanian, Ghavam G. Shahidi
  • Patent number: 11016731
    Abstract: Disclosed embodiments relate to performing floating-point (FP) arithmetic. In one example, a processor is to decode an instruction specifying locations of first, second, and third floating-point (FP) operands and an opcode calling for accumulating a FP product of the first and second FP operands with the third FP operand, and execution circuitry to, in a first cycle, generate the FP product having a Fuzzy-Jbit format comprising a sign bit, a 9-bit exponent, and a 25-bit mantissa having two possible positions for a JBit and, in a second cycle, to accumulate the FP product with the third FP operand, while concurrently, based on Jbit positions of the FP product and the third FP operand, determining an exponent adjustment and a mantissa shift control of a result of the accumulation, wherein performing the exponent adjustment concurrently enhances an ability to perform the accumulation in one cycle.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Amit Gradstein, Simon Rubanovich, Zeev Sperber
  • Patent number: 11018692
    Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 25, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Anirban Nag, Naveen Muralimanohar, Paolo Faraboschi
  • Patent number: 11010662
    Abstract: Massively parallel neural inference computing elements are provided. A plurality of multipliers is arranged in a plurality of equal-sized groups. Each of the plurality of multipliers is adapted to, in parallel, apply a weight to an input activation to generate an output. A plurality of adders is operatively coupled to one of the groups of multipliers. Each of the plurality of adders is adapted to, in parallel, add the outputs of the multipliers within its associated group to generate a partial sum. A plurality of function blocks is operatively coupled to one of the plurality of adders. Each of the plurality of function blocks is adapted to, in parallel, apply a function to the partial sum of its associated adder to generate an output value.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Steven K. Esser, Myron D. Flickner, Jennifer Klamo, Dharmendra S. Modha, Hartmut Penner, Jun Sawada, Brian Taba
  • Patent number: 11010635
    Abstract: A method for processing electronic data includes the steps of transforming the electronic data to a matrix representation including a plurality of matrices; decomposing the matrix representation into a series of matrix approximations; and processing, with an approximation process, the plurality of matrices thereby obtaining a low-rank approximation of the plurality of matrices.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 18, 2021
    Assignee: City University of Hong Kong
    Inventors: Hing Cheung So, Wen-Jun Zeng, Jiayi Chen, Abdelhak M. Zoubir
  • Patent number: 11010131
    Abstract: An integrated circuit may include a floating-point adder. The adder may be implemented using a dual-path adder architecture having a near path and a far path. The near path may include a leading zero anticipator (LZA), a comparison circuit for comparing an exponent value to an LZA count, and associated circuitry for handling subnormal numbers. The far path may include a subtraction circuit for computing the difference between a received exponent value and a minimum exponent value, at least two shifters for shifting far greater and far lesser mantissa values in parallel, and associated circuitry for handling subnormal numbers. The adder may be dynamically configured to support a first mode that processes FP16 at inputs and outputs, a second mode that processes modified FP16? inputs, and a third mode that processes FP16? at inputs and outputs.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Bogdan Pasca
  • Patent number: 11003985
    Abstract: Provided is a convolutional neural network system including a data selector configured to output an input value corresponding to a position of a sparse weight from among input values of input data on a basis of a sparse index indicating the position of a nonzero value in a sparse weight kernel, and a multiply-accumulate (MAC) computator configured to perform a convolution computation on the input value output from the data selector by using the sparse weight kernel.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: May 11, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Kyu Kim, Byung Jo Kim, Seong Min Kim, Ju-Yeob Kim, Mi Young Lee, Joo Hyun Lee
  • Patent number: 10997277
    Abstract: An integrated circuit device such as a neural network accelerator can be programmed to select a numerical value based on a multinomial distribution. In various examples, the integrated circuit device can include an execution engine that includes multiple separate execution units. The multiple execution units can operate in parallel on different streams of data. For example, to make a selection based on a multinomial distribution, the execution units can be configured to perform cumulative sums on sets of numerical values, where the numerical values represent probabilities. In this example, to then obtain cumulative sums across the sets of numerical values, the largest values from the sets can be accumulated, and then added, in parallel to the sets. The resulting cumulative sum across all the numerical values can then be used to randomly select a specific index, which can provide a particular numerical value as the selected value.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 4, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Yu Zhou, Vignesh Vivekraja, Ron Diamant
  • Patent number: 10997275
    Abstract: A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a Boolean function on all associated columns, using the results to calculate a product between the vector-matrix pair of rows, and writing the product to an R-product-j row in the array.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 4, 2021
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Pat Lasserre
  • Patent number: 10990355
    Abstract: The present innovative solution solves the problem of generating pseudo-random numbers that have practically infinite period, while requiring limited processing resources and operating significantly faster that known pseudo-random number generators. A sequence of pseudo-random numbers is created by a linear congruential generator using a large seed number and the sequence is used to create a big number. The big number is formed by raising each of at least two pseudo-random numbers and their sum to the same power. The big number is then selectively split into a sequence of aperiodic pseudo-random numbers which are output for use in any suitable application and for seeding the present generator.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 27, 2021
    Inventor: Panagiotis Andreadakis
  • Patent number: 10984074
    Abstract: Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row M and column K of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Srinivasan Narayanamoorthy, Nadathur Rajagopalan Satish, Alexey Suprun, Kenneth J. Janik
  • Patent number: 10983756
    Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 20, 2021
    Assignee: Imagination Technologies Limited
    Inventor: Leonard Rarick
  • Patent number: 10977339
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 13, 2021
    Assignee: Mythic, Inc.
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
  • Patent number: 10970201
    Abstract: A system, apparatus and method for utilizing a transpose function to generate a two-dimensional array from three-dimensional input data. The use of the transpose function reduces redundant elements in the resultant two-dimensional array thereby increasing efficiency and decreasing power consumption.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 6, 2021
    Assignee: Arm Limited
    Inventor: Paul Nicholas Whatmough
  • Patent number: 10963220
    Abstract: An N×N multiplier may include a N/2×N first multiplier, a N/2×N/2 second multiplier, and a N/2×N/2 third multiplier. The N×N multiplier receives two operands to multiply. The first, second and/or third multipliers are selectively disabled if an operand equals zero or has a small value. If the operands are both less than 2N/2, the second or the third multiplier are used to multiply the operands. If one operand is less than 2N/2 and the other operand is equal to or greater than 2N/2, the first multiplier is used or the second and third multipliers are used to multiply the operands. If both operands are equal to or greater than 2N/2, the first, second and third multipliers are used to multiply the operands.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 30, 2021
    Inventors: Ilia Ovsiannikov, Ali Shafiee Ardestani, Joseph Hassoun, Lei Wang
  • Patent number: 10956536
    Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Patent number: 10949495
    Abstract: A device configured to emulate a correlithm object system includes a memory that stores a node table. The node table identifies a plurality of source correlithm objects and a corresponding plurality of target correlithm objects. A node receives a first input correlithm object associated with a first timestamp, computes distances between the first input correlithm object and each of the source correlithm objects in the node table, and identifies a first source correlithm object from the node table with the shortest distance. The node identifies a first target correlithm object from the node table linked with the identified first source correlithm object, and outputs the first target correlithm object. The memory stores a node output table that identifies the first target correlithm object associated with the first source correlithm object, the first timestamp, and the computed distance between the first input correlithm object and the first source correlithm object.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 10949494
    Abstract: A correlithm object processing system uses one or more mobile correlithm object devices to emulate the functionality of one or more of sensors, nodes, and actors. The mobile correlithm object devices may be deployed to different parts of a system or network to perform particular tasks. The mobile correlithm object devices may periodically communicate with one another or with other elements of the correlithm object processing system.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence