Patents Examined by Andrew Caldwell
  • Patent number: 10089112
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a fuse array that stores configuration data.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 2, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10068652
    Abstract: The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Glen E. Hush, Richard C. Murphy
  • Patent number: 10067745
    Abstract: A method of generating a random number that involves applying pulses of energy to amplify a quantum mechanical vacuum fluctuation to generate one or more macroscopic fields having one or more physical properties (e.g. phase or energy) that are random and measurable, and, measuring at least one of the physical properties to obtain a value for the physical property, the value of the physical property being a random number. Measuring the phase of a Stokes signal generated in a transient Raman scattering process is one way of generating the random number as the phase of the Stokes signal is random. This method can produce random numbers faster than prior art methods as the real numbers generated can be converted to binary to produce more than one random bit and the measurement process itself is faster permitting more rapid data collection rates and more rapid turn-on times.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 4, 2018
    Assignee: National Research Council of Canada
    Inventors: Benjamin J. Sussman, Philip J. Bustard
  • Patent number: 9934000
    Abstract: An apparatus for balancing consumption of random data, comprising an entropy manager operable to: responsive to receipt of a request for random data, monitor one or more events associated with a plurality of entities and access one or more rules; determine whether a higher level of entropy associated with the random data is required by analyzing the one or more events in accordance with the one or more rules; responsive to a determination that a higher level of entropy is not required, set an entropy state associated with the entropy to a lower level of entropy and obtain random data from an entropy source having a lower level of entropy; and responsive to a determination that a higher level of entropy is required, switch an entropy state associated with the entropy to a higher level of entropy and obtain random data from an entropy source having a higher level of entropy.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: David Sherwood, James William Walker, Travis Walton
  • Patent number: 9928067
    Abstract: Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Xueliang Zhong, Jianhui Li, Jian Ping Jane Chen, Gang Wang, Yi Qian, Huifeng Gu
  • Patent number: 9904551
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9898295
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9898287
    Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 20, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sooraj Puthoor, Bradford M. Beckmann, Dmitri Yudanov
  • Patent number: 9891914
    Abstract: An apparatus and method for performing an efficient scatter operation. For example, one embodiment of a processor comprises: an allocator unit to receive a scatter operation comprising a number of data elements and responsively allocate resources to execute the scatter operation; a memory execution cluster comprising at least a portion of the resources to execute the scatter operation, the resources including one or more store data buffers and one or more store address buffers; and a senior store pipeline to transfer store data elements from the store data buffers to system memory using addresses from the store address buffers prior to retirement of the scatter operation.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Ramon Matas, Alexey P. Suprun, Roger Gramunt, Chung-Lun Chan, Rammohan Padmanabhan
  • Patent number: 9886362
    Abstract: A method for checking the integrity of a program executed by an electronic circuit and including at least one conditional jump, wherein: a first value is updated for any instruction which does not correspond to a jump instruction; a second value is updated with the first value for each conditional jump instruction; and the second value is compared with a third value, calculated according to the performed conditional jumps.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: February 6, 2018
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Gilles Van Assche, Ronny Vankeer
  • Patent number: 9880849
    Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 30, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Matthew Ashcraft, Richard W. Thaik
  • Patent number: 9875105
    Abstract: Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 23, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell Boggs, Magnus Ekman
  • Patent number: 9875215
    Abstract: Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 23, 2018
    Assignee: D-Wave Systems Inc.
    Inventors: William Macready, Aidan Patrick Roy
  • Patent number: 9858082
    Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Timothy J. Slegel
  • Patent number: 9851978
    Abstract: Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained. There are instructions only restricted in constrained transactions, and there are instructions that are selectively restricted for given transactions based on controls specified on instructions used to initiate the transactions.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Timothy J. Slegel
  • Patent number: 9841978
    Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 12, 2017
    Assignee: Sony Corporation
    Inventors: Hirokazu Hanaki, Satoshi Takashima
  • Patent number: 9841974
    Abstract: A processor including a register file having a plurality of registers, and configured for out-of-order instruction execution, further includes a renamer unit that produces generation numbers that are associated with register file addresses to provide a renamed version of a register that is temporally offset from an existing version of that register rather than assigning a non-programmer-visible physical register as the renamed register.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 12, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sophie Wilson, John Redford, Tariq Kurd
  • Patent number: 9830164
    Abstract: A system and method for efficiently processing instructions in hardware parallel execution lanes within a processor. In response to a given divergent point within an identified loop, a compiler arranges instructions within the identified loop into very large instruction words (VLIW's). At least one VLIW includes instructions intermingled from different basic blocks between the given divergence point and a corresponding convergence point. The compiler generates code wherein when executed assigns at runtime instructions within a given VLIW to multiple parallel execution lanes within a target processor. The target processor includes a single instruction multiple data (SIMD) micro-architecture. The assignment for a given lane is based on branch direction found at runtime for the given lane at the given divergent point. The target processor includes a vector register for storing indications indicating which given instruction within a fetched VLIW for an associated lane to execute.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 28, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Reza Yazdani
  • Patent number: 9823929
    Abstract: A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register field) executes, the queue is searched for any entries that contain instructions that depend upon the executed write instruction. Each such entry stores the value of the register field at the time the instruction in the entry was processed. If such an entry is found in the queue and its stored value of the register field does not match the value that the write instruction wrote to the register field, then the processor flushes the pipeline and restarts at a state so as to correctly execute the instruction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Daren Eugene Streett, Brian Michael Stempel, Thomas Philip Speier, Rodney Wayne Smith, Michael Scott McIlvaine, Kenneth Alan Dockser, James Norris Dieffenderfer
  • Patent number: 9817662
    Abstract: The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, which accounts for both rounding and cancellation errors, has two parts, the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the real value represented are determined from the truncated floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). The true, real value is absolutely contained by the first and second bounds. The allowed loss (optionally programmable) of significant bits provides a fail-safe, real-time notification of loss of significant bits.
    Type: Grant
    Filed: October 23, 2016
    Date of Patent: November 14, 2017
    Inventor: Alan A Jorgensen