Abstract: Comparator circuitry comprises carry-save-addition (CSA) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the CSA circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.

Abstract: A processing system includes a program processor for executing a program, and a dedicated processor for executing operations of a particular type (e.g. vector processing operations). The program processor uses an interfacing module and a group of two or more register banks to offload operations of the particular type to the dedicated processor for execution thereon. While the dedicated processor is accessing one register bank for executing a current operation, the interfacing module can concurrently load data for a subsequent operation into a different one of the register banks. The use of multiple register banks allows the dedicated processor to spend a greater proportion of its time executing operations.

Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.

Abstract: A device that includes a sensor engine configured to receive an input signal, to identify a real world value entry in a sensor table based on the input signal, to identify an input correlithm object linked with the real world value entry, and to send the identified input correlithm object to a node engine. The node engine is configured to identify a source correlithm object from a node table with the shortest distance from the input correlithm object, to identify a target correlithm object linked with the identified source correlithm object, and to send the identified target correlithm object to an actor engine. The actor engine is configured to identify an output correlithm object from an actor table with the shortest distance from the target correlithm object, to identify a real world output value linked with the identified output correlithm object, and to output the real world output value.

Abstract: A navigation device including a digital filter configured to smooth tracking is provided. The digital filter is configured to sequentially receive input data and output a tap sum, and calculate a quotient and a remainder by dividing an accumulation value with an average number, wherein the remainder is feedback to the tap sum for updating the accumulation value and the quotient is configured as output data.

Abstract: Processor instructions for determining two minimum and two maximum values and associated apparatus and methods. The instructions include various 2MIN instructions for determining the two smallest values among three or four input values and 2MAX instructions for determining the two largest values among three or four input values. The 2MIN instructions employ two operands, with the first operand in some of the variations storing concatenated min1 and min2 values in a first register and a scr2 comparison value or two src2 concatenated src2 values in a second register. Comparators are used to implement hardware logic for determining whether the scr2 value(s) is/are less than each of min1 and min2. Based on the hardware logic, the smallest two values among min1, min2, and src2 (or both src2 values) are stored as concatenated values in the first register. The 2MAX instructions are implemented in a similar manner, except the comparisons are whether the scr2 value(s) is/are greater than each of max1 and max2 values.

Abstract: Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain.

Abstract: A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.

Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.

Abstract: A method for computing trigonometric functions, performed by an ALU (Arithmetic Logic Unit) in coordination with an SFU (Special Function Unit), is introduced to contain at least the following steps. The ALU computes a remainder r and a reduction value x* corresponding to an input parameter x. The SFU computes an intermediate function f(x*) corresponding to the reduction value x*. The ALU computes a multiplication of the reduction value x* by the intermediate function f(x*) as the computation result of a trigonometric function.

Abstract: Provided is an event signal processing method and apparatus. The event signal processing method includes acquiring, from an event based sensor, coordinates of an active pixel corresponding to an event and a timestamp corresponding to the event; mapping the event to a target voxel included in a three-dimensional (3D) grid based on the coordinates of the active pixel and the timestamp; and updating a value of the target voxel based on the event.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the multi-slice processor is configured to dynamically cancel partial load operations by, among other steps, receiving a load instruction requesting multiple portions of data; receiving a load instruction requesting multiple portions of data; determining that a load of one portion of the requested multiple portions is unavailable to be issued; and responsive to determining that the load of the one portion of the requested multiple portions is unavailable to be issued, delaying issuance of the load instruction.

Abstract: An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation, and in addition provides reduce and round circuitry that generates from a supplied floating point value a modified floating point value to be input to the argument reduction circuitry. The reduce and round circuitry is arranged to modify a significand of the supplied floating point value, based on a specified value N, in order to produce a truncated significand with a specified rounding applied, the truncated significand being N bits shorter than the significand of the supplied floating point value, and then being used as a significand for the modified floating point value. The specified value N is chosen such that the argument reduction operation performed using the modified floating point value will inhibit roundoff error in a result of the argument reduction operation.

Abstract: An object of the invention is to speed up processing of adding floating-point numbers. A floating-point adder includes: a first register configured to store a first fixed-point number having a predetermined number of digits corresponding to a result of accumulation of a plurality of floating-point numbers; a first conversion unit configured to convert an input first floating-point number into a second fixed-point number having the predetermined number of digits; a second register configured to store the second fixed-point number; an adder configured to add the second fixed-point number stored in the second register and the first fixed-point number stored in the first register, and store a result of the addition in the first register as the first fixed-point number; and a second conversion unit configured to convert the first fixed-point number into a second floating-point number, and output the second floating-point number.

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract: A processor includes a back end to execute decoded instructions and a front end. The front end includes two decode clusters and circuitry to receive data elements representing undecoded instructions, in program order, and to direct subsets of the data elements to the decode clusters. An IP generator directs one subset of data elements to the first cluster, detects a condition indicating that a load balancing action should be taken, and directs a subset of data elements immediately following the first subset in program order to the first or second decode cluster dependent on the action taken. The action may include annotating a BTB entry, inserting a fake branch in the BTB, forcing a cluster switch, or suppressing a cluster switch. The detected condition may be a predicated taken branch or an annotation thereof, or a heuristic based on a queue state, a count of uops, or a latency value.

Abstract: A data processing system includes instruction decoder circuitry responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry performs a right shift upon at least part of the input number and left shifting circuitry performs a left shift of at least part of the input number. Selection circuitry serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.

Abstract: Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.