Abstract: Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row M and column K of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.

Abstract: The invention introduces a method for calculating floating-point operands, which contains at least the following steps: receiving an FP (floating-point) operand in a first format from a source register, wherein the first format is one of a group of first formats of different kinds; converting the FP operand in the first format into an FP operand in a second format; generating a calculation result in the second format by calculating the FP operand in the second format; converting the calculation result in the second format into a calculation result in the first format; and writing-back the calculation result of the first format.

Abstract: This method for the non-linear estimation of no more than two mixed signals from separate sources, the time/frequency representation of which shows an unknown non-zero proportion of zero components, using an array made up of P>2 antennas, when the directional vectors U and V of the sources emitting these signals are additionally known or estimated, includes the following steps: a) Calculating the successive discrete Fourier transforms of the signal received by the antennas and sampled to obtain a time-frequency P-vector grid of the signal; each element of the grid being referred to as a box and containing a complex vector X forming a measurement; b) For each box, calculating the conditional expectation estimator of the signal, or of the signals, from the measurement X and an a priori probability density for the signals that is a Gaussian mixture.

Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew?1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.

Abstract: A neural network engine comprises a plurality of floating point multipliers, each having an input connected to an input map value and an input connected to a corresponding kernel value. Pairs of multipliers provide outputs to a tree of nodes, each node of the tree being configured to provide a floating point output corresponding to either: a larger of the inputs of the node; or a sum of the inputs, one output node of the tree providing a first input of an output module, and one of the multipliers providing an output to a second input of the output module. The engine is configured to process either a convolution layer of a neural network, an average pooling layer or a max pooling layer according to the kernel values and whether the nodes and output module are configured to output a larger or a sum of their inputs.

Abstract: The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a controller configured to cause: summing, in parallel, of data values corresponding to respective ones of a plurality of first vectors stored in memory cells of the array as a data value sum representing a population count thereof, wherein a second vector is stored as the plurality of first vectors, and wherein each first vector of the plurality of first vectors is stored in respective memory cells of the array that are coupled to a respective sense line of a plurality of sense lines; and iteratively summing, in parallel, of data value sums corresponding to the plurality of first vectors to provide a single data value sum corresponding to the second vector.

Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.

Abstract: A function generator provides a first signal unit for the delivery of a first signal at a first output. The function generator provides a second signal unit for the delivery of a second signal at a second output. The function generator provides a calibration unit for the generation of a test signal, wherein the test signal can be supplied to the first signal unit and/or to the second signal unit. A comparison unit is connected downstream of the first signal unit and/or the second signal unit. The comparison unit compares the test signal delivered at the first output and/or at the second output with a calibration signal, wherein the output signal of the comparison unit can be supplied to the calibration unit.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

Abstract: Processing circuitry is provided for comparing a number of adjacent widths having a common value and extending from a starting position within an input number with a runlength specified by a variable number. The circuitry includes a mask generator for generating a mask value in dependence upon the variable number, combination circuitry for performing a logical combination operation upon respective bits within the input number starting from the starting position and corresponding bits within the mask value so as to generate an intermediate value. Result circuitry then generates a result indicative of whether or not the number of adjacent bits is less than or equal to the run length in dependence upon a determination if any bits within the intermediate value have a predetermined value.

Abstract: A method for matrix by vector multiplication, applied in an artificial neural network system, is disclosed. The method comprises: compressing a plurality of weight values in a weight matrix and indices of an input vector into a compressed main stream; storing M sets of synapse values in M memory devices; and, performing reading and MAC operations according to the M sets of synapse values and the compressed main stream to obtain a number M of output vectors. The step of compressing comprises: dividing the weight matrix into a plurality of N×L blocks; converting entries of a target block and corresponding indices of the input vector into a working block and an index matrix; removing zero entries in the working block; shifting non-zero entries row-by-row to one of their left and right sides in the working block; and, respectively shifting corresponding entries in the index matrix.

Abstract: An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.

Abstract: A method for compressing multiple original convolution parameters into a convolution operation chip includes steps of: determining a range of the original convolution parameters; setting an effective bit number for the range; setting a representative value, wherein the representative value is within the range; calculating differential values between the original convolution parameters and the representative value; quantifying the differential values to a minimum effective bit to obtain a plurality of compressed convolution parameters; and transmitting the effective bit number, the representative value and the compressed convolution parameters to the convolution operation chip.

Abstract: A random number acquiring unit 15 obtains a first sequence that comprises values of digits of a random number represented by a binary number as elements. A logical product arithmetic unit 16 obtains a third sequence that is results of elementwise logical product operation between the first sequence and a second sequence that comprises values of digits of one or more Mersenne numbers represented by one or more binary numbers and a zero value as elements.

Abstract: A navigation device including a digital filter configured to smooth tracking is provided. The digital filter is configured to sequentially receive input data and output a tap sum, and calculate a quotient and a remainder by dividing an accumulation value with an average number, wherein the remainder is feedback to the tap sum for updating the accumulation value and the quotient is configured as output data.

Abstract: Unpredictable random numbers are used to provide the parameter values and seeds for a parameterized random number generator, thereby providing forensic reproducibility of a simulation. The values generated unpredictably to provide the parameters and seeds for the random number generator are stored so that the same random numbers can be utilized for a subsequent computation in the simulation.

Abstract: In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.

Abstract: Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero.

Abstract: A computational device includes an input memory, which receives a first array of input numbers having a first precision represented by N bits. An output memory stores a second array of output numbers having a second precision represented by M bits, M<N. Quantization logic reads the input numbers from the input memory, extracts from each input number a set of M bits, at a bit offset within the input number that is indicated by a quantization factor, and writes a corresponding output number based on the extracted set of bits to the second array in the output memory. A quantization controller sets the quantization factor so as to optimally fit an available range of the output numbers in the second array to an actual range of the input numbers in the first array in extraction of the M bits from the input numbers.

Abstract: Computational apparatus includes a memory, which contains first and second input matrices of input data values, having at least three dimensions including respective heights and widths in a predefined sampling space and a common depth in a feature dimension, orthogonal to the sampling space. An array of processing elements each perform a multiplication of respective first and second input operands and to accumulate products of the multiplication to generate a respective output value. Data access logic extracts first and second pluralities of vectors of the input data values extending in the feature dimension from the first and second input matrices, respectively, and distributes the input data values from the extracted vectors in sequence to the processing elements so as to cause the processing elements to compute a convolution of first and second two-dimensional matrices composed respectively of the first and second pluralities of vectors.