Abstract: A disk storage unit according to the present invention has a head driving member for driving a float type head so that a head can be separated from a disk while the disk stops rotating and approached to the disk when the disk starts to rotate, and a head driving mechanism for driving the head driving member. Incidentally, the head driving mechanism may be made of shape memory alloy or piezoceramic.

Abstract: A noise filter to eliminate short, multiple pulses output from an address transition detection ("ATD") circuit caused by address line noise occurring during a read operation of a nonvolatile semiconductor memory. The ATD circuit includes a pulse summation circuit. Each address line sends an input pulse to the pulse summation circuit when the address bit corresponding to the address line changes. The pulse summation circuit adds and extends the input pulses to form output pulses. Pulse extension is performed by a delay chain formed by NAND and NOR gates. Each output pulse begins after a first predetermined time from the leading edge of an input pulse. The delay chain is set on the leading edge of each input pulse. The trailing edge of each input pulse determines when the delay chain will begin to reset. The extended pulse ends after a delay caused by the delay chain unless a subsequent pulse leading edge occurs within a second predetermined time from each trailing edge.

Abstract: A decoder circuit is implemented by emitter coupled logic circuits, and comprises decoding stages respectively supplied with combinations of component bits, driver stages respectively associated with the decoding stages for driving capacitive loads, and bypassing circuits coupled between the output terminals of the driver stages and a common constant current source, wherein each of the bypassing circuits is implemented by a bipolar transistor having a collector to emitter current path between the associated output terminal and the common constant current source and a base node coupled through a resistive element with the associated output terminal so that discharge current flows through the collector to emitter current path until all the electric charges are evacuated from the capacitive load, thereby increasing operation speed.

Abstract: An integrated circuit output driver circuit is disclosed. The output driver varies the impedance of the driver circuit based upon the output voltage level present on the output pad. In that manner, the output driver circuit compensates for process variations and operating conditions. Two FETs are used in parallel to pull the voltage level of the output pad down. One FET is turned on and left on whenever a low voltage level in the output pad is desired. The other smaller FET is used to vary the total impedance of the driver by using feedback from the signal pad to sense when the pad voltage has reached a threshold level at that point the second FET is turned off.

Abstract: A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential.

Abstract: Prior-art high speed TTL-to-CMOS input buffers consume a large amount of power supply current through the input transistors when the input voltage is held at a mid-range level between V.sub.DD and V.sub.SS (e.g., 2.0 volts). The inventive input buffer includes a resistance in series with the p-channel pull-up transistor on the input inverter, in order to limit this current. In addition, to retain high operating speed, a p-channel shunt transistor is placed in parallel with the resistance, and controlled by the buffer output signal. This shunt transistor effectively bypasses the resistance from the circuit when the buffer output goes low, thereby providing high operating speed.

Abstract: The present inventor provides a magnetic disk apparatus that has a moving unit, a magnetic head and a wiring plate that electrically insulates the magnetic head and the moving unit. The moving unit is configured so as to be movable in a direction substantially parallel to a surface of the magnetic disk. The magnetic head records and/or reproduces signals on and/or from the surface of the magnetic disk supported on a electrically conductive flexible member. The wiring plate is configured from an insulated member sandwiched between the moving unit and the flexible member and a wiring portion that is formed on the flexible member and electrically connected to the magnetic head.

Abstract: A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a field programmable logic array (FPLA) using a dedicated product term for macrocell control. Particularly, the macrocells contain a faster, more flexible, and exclusive feedback line as well as an exclusive external-input line from an input/output (I/O) pad for a registered mode of operation. Moreover, there is a registered mode macrocell which has 1) a feedback path for the registered mode signals which is activated even when the I/O pad driver is disabled, 2) an input path, to the logic circuitry, over an I/O pad, 3) a feedback path for the registered mode signals while outputting the same registered mode signals, and 4) a feedback path which avoids the unnecessary signal noise emanating from the use of a 3-state device or output driver.

Abstract: This invention describes the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The invention further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels.

Abstract: An integrated circuit or a gate array having a logic gate block functioning in accordance with circuits defined in the interior and data, which circuit includes an analog circuit, a passive electronic element array capable of changing circuit parameters of the analog circuit, an analog switch element capable of switching an analog signal by a digital signal, a variable characteristics analog circuit capable of defining and changing the circuit arrangement and the circuit characteristics, and a digital circuit capable of controlling the defining and the changing of the circuitry.

Abstract: A programmable logic device (PLD) is disclosed which has an output macrocell. The macrocell selectively produces either a registered and inverted registered set of signals, or a combinatorial or inverted combinatorial set of signals, but not both set of signals.

Abstract: An automatic system for adjusting the output impedance of fast CMOS drivers, wherein the output impedance of a plurality of slaved drivers is adjusted by a circuit for measuring and correcting mismatch between the output impedance of one of the drivers, taken as reference and dedicated for this purpose, and the impedance at the input of a reference transmission line, equal in geometry to the lines connected to the other drivers. The voltage measured at the far end of the reference line is sent to a differential amplifier where it is compared with the supply voltage of the final driving stage. According to the comparison result at specific time intervals, a signal is supplied to the regulator which supplies power to the penultimate driving stage, thereby controlling the resistance of the driver to match the line impedance.

Abstract: A rotary drum device includes a brush unit for supplying a signal or a current to a rotary portion. The rotary drum device has a guide portion along which the brush unit can move such that a contact force of a brush at the contacting point between the rotary portion and the brush can be maintained substantially constant.

Abstract: A sense amplifier circuit for use in a ROM comprises, an excess charge detecting circuit for producing a detection output when a potential of a bit line exceeds a normal value, and an excess charge discharging circuit which operates in response to said excess charge detecting circuit for discharging a bit line charge and for returning the bit line potential to the normal value.The excess charge detecting circuit and the excess charge discharge circuit can be realized by a diode connected transistor connected between the bit line and an inverter of the sense amplifier. When the bit line potential is about to exceed the predetermined value, the transistor turns on to prevent the bit line potential from exceeding the predetermined value.

Abstract: A stackable linear actuator using flat, planar carriages. Each carriage is formed of two thin fiber reinforced outer surfaces having a low density composite core between each of the outer surfaces. A flat single layer coil is mounted within the composite core. The carriages are mounted for relative movement in a vertical stack. Between each carriage is a set of permanent magnets of opposing polarity. The sets of magnets are aligned so that magnets of similar polarity are aligned vertically. A steel plate is attached at the top of the stack. Another steel plate is attached to the bottom of the stack. These plates shunt the magnetic flux to form a continuous loop of magnetic flux through the entire stack. The carriages are operated by supplying the coils with current of varying intensity and polarity.

Abstract: In a high speed logic circuit using a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer, two base electrodes making contact with the base layer are disposed so as to put a collector electrode, which is electrically in contact with the collector layer, therebetween. The base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using the two-dimensional carriers as an active layer. The high speed logic circuit is so constructed that one of the base electrodes of the bipolar transistor is an input terminal; the other is connected with a power supply; the emitter is grounded; and the collector is an output terminal.

Abstract: The present invention discloses a semiconductor output circuit with temperature compensated noise control. The output circuit of the present invention presents an increase in speed, a reduction in power consumption, and a reduction in noise level as compared with the prior art temperature compensated noise control output circuits. These advantages are obtained by utilizing the present invention's current control means which current control means is driven by a temperature compensation circuit.

Abstract: A semiconductor logical device provides one or a plurality of first field effect transistor(s) which perform a switching operation in accordance with an input signal input to a gate contact thereof, a first element which is constituted by a field effect transistor whose gate and source contacts are subjected to short-circuit, and which is connected as a load of the first field effect transistor, a second element which is constituted by a field effect transistor whose gate and source contacts are subjected to short-circuit and which is connected in series to the first element to act as a load of the first field effect transistor, a source follower circuit for power-amplifying a signal which is generated in the gate-source contact of the first element, and a second field effect transistor whose drain contact is connected to the gate-source contact of the second element, whose source contact is connected to an anode contact of a diode which generates a desired voltage, and to whose gate contact an output signal

Abstract: A self latching input buffer is disclosed which includes an address input buffer which is responsive to a first clock signal so as to produce an output signal. data in the input buffer is latched in connection with the receipt of a second clock signal which is produced by a detector which is responsive to the output signal.

Abstract: A plurality of tristate circuits (TSG1, TSG2, TSG3) each include an input circuit (NAND1, NOR1; NAND2, NOR2; NAN3, NOR3) for receiving first and second control signals (.phi.goe1*, in1; .phi.goe2*, in2; .phi.goe3*, in3) and a tristate output circuit (Q1p, Q1n; Q2p, Q2n; Q3n). The input circuits further receiving a test signal (TEST*). The tristate circuits each include a tristate output (OT1; OT2; OT3) which connects the output circuit to a signal line (SL). The signal line is connected with a test output circuit (Ru, Q4p, Q4n, Rd). The tristate output circuits each include a MOSFET (Q1p; Q2p; Q3p) for selectively connecting the tristate output (OT1; OT2; OT3) with a power supply terminal (Vdd) and a MOSFET (Q1n; Q2n; Q3N) for connecting the tristate output with a ground voltage level (Vss).